s29as008j Meet Spansion Inc., s29as008j Datasheet - Page 13

• Manufacturer Part Number: s29as008j
• Description: 8 Megabit 1 M X 8-bit/512 K X 16-bit Cmos 1.8 Volt-only Boot Sector Flash Memory
• Manufacturer: Meet Spansion Inc.

7.
7.1
7.2
June 6, 2008 S29AS008J_00_03
Device Bus Operations
Word/Byte Configuration
Requirements for Reading Array Data
This section describes the requirements and use of the device bus operations, which are initiated through the
internal command register. The command register itself does not occupy any addressable memory location.
The register is composed of latches that store the commands, along with the address and data information
needed to execute the command. The contents of the register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the device.
inputs and control levels they require, and the resulting output. The following subsections describe each of
these operations in further detail.
Legend
L = Logic Low = V
Notes
1. Addresses are A18:A0 in word mode (BYTE# = V
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See
3. If WP# = V
The BYTE# pin controls whether the device data I/O pins DQ15–DQ0 operate in the byte or word
configuration. If the BYTE# pin is set at logic 1, the device is in word configuration, DQ15–DQ0 are active and
controlled by CE# and OE#.
If the BYTE# pin is set at logic 0, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used
as an input for the LSB (A-1) address function.
To read array data from the outputs, the system must drive the CE# and OE# pins to V
control and selects the device. OE# is the output control and gates array data to the output pins. WE# should
remain at V
The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory content occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses
on the device address inputs produce valid data on the device data outputs. The device remains enabled for
read access until the command register contents are altered.
See
timing specifications and to
on page 41
Read
Write (Program/Erase)
Standby
Output Disable
Reset
Sector Protect
Sector Unprotect
(Note 2)
Temporary Sector
Unprotect
Unprotection on page
whether they were last protected or unprotected. If WP# = V
D a t a
Reading Array Data on page 28
Operation
IL
IH
represents the active current specification for reading array data.
, the two outermost boot sectors remain protected. If WP# = V
(Note 2)
. The BYTE# pin determines whether the device outputs array data in words or bytes.
S h e e t
IL
, H = Logic High = V
19.
V
0.2 V
CE#
CC
X
X
L
L
L
L
L
±
( A d v a n c e
OE#
Figure 18.1 on page 43
H
H
H
H
L
X
X
X
IH
Table 7.1 S29AS008J Device Bus Operations
, V
WE#
H
H
L
X
X
L
L
X
ID
= 9.0–11.0 V, X = Don’t Care, A
for more information. Refer to the AC
RESET#
S29AS008J
V
0.2 V
V
V
V
CC
IH
H
H
H
L
ID
ID
ID
), A18:A-1 in byte mode (BYTE# = V
±
I n f o r m a t i o n )
(Note 3)
WP#
HH
X
H
X
X
X
H
H
, all sectors are unprotected.
for the timing diagram. I
A6 = H, A3 = A2 = L,
A6 = L, A3 = A2 = L,
Sector Address,
Sector Address,
A1 = H, A0 = L
A1 = H, A0 = L
Addresses
IH
Table 7.1
IN
(Note 1)
, the two outermost boot sector protection depends on
= Address In, D
A
A
A
X
X
X
IN
IN
IN
IL
lists the device bus operations, the
).
Read Operations on page 43
IN
High-Z
High-Z
High-Z
DQ0–
D
CC1
DQ7
D
D
D
D
= Data In, D
OUT
IN
IN
IN
IN
in
DC Characteristics
BYTE#
High-Z
High-Z
High-Z
D
= V
D
D
OUT
X
X
IN
IN
IH
OUT
IL
. CE# is the power
Sector Protection/
= Data Out
DQ8–DQ15
DQ8–DQ14 = High-Z,
DQ15 = A-1
BYTE#
High-Z
High-Z
High-Z
High-Z
= V
X
X
IL
for
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