s29al016m Meet Spansion Inc., s29al016m Datasheet - Page 15

• Manufacturer Part Number: s29al016m
• Description: 16 Megabits 2m X 8-bits / 1m X 16-bits
• Manufacturer: Meet Spansion Inc.

October 11, 2006 S29AL016M_00_A7
Automatic Sleep Mode
RESET#: Hardware Reset Pin
Output Disable Mode
The device enters the CMOS standby mode when the CE# and RESET# pins are
both held at V
V
will be in the standby mode, but the standby current will be greater. The device
requires standard access time (t
of these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws ac-
tive current until the operation is completed.
In the
specification.
The automatic sleep mode minimizes Flash device energy consumption. The
device automatically enables this mode when addresses remain stable for t
30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE#
control signals. Standard address access timings provide new data when
addresses are changed. While in sleep mode, output data is latched and always
available to the system. I
automatic sleep mode current specification.
The RESET# pin provides a hardware method of resetting the device to reading
array data. When the system drives the RESET# pin to V
t
data output pins, and ignores all read/write attempts for the duration of the RE-
SET# pulse. The device also resets the internal state machine to reading array
data. The operation that was interrupted should be reinitiated once the device is
ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held
at V
at V
The RESET# pin may be tied to the system reset circuitry. A system reset would
thus also reset the Flash memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin re-
mains a “0” (busy) until the internal reset operation is complete, which requires
a time of t
RY/BY# to determine whether the reset operation is complete. If RESET# is as-
serted when a program or erase operation is not executing (RY/BY# pin is “1”),
the reset operation is completed within a time of t
Algorithms). The system can read data t
Refer to the
for the timing diagram.
When the OE# input is at V
are placed in the high impedance state.
RP
IH
, the device immediately terminates any operation in progress, tristates all
.) If CE# and RESET# are held at V
IL
SS
±0.3 V, the device draws CMOS standby current (I
but not within V
DC Characteristics
READY
AC Characteristics
CC
± 0.3 V. (Note that this is a more restricted voltage range than
(during Embedded Algorithms). The system can thus monitor
D a t a
SS
±0.3 V, the standby current will be greater.
IH
table, I
CC4
, output from the device is disabled. The output pins
S h e e t
in the
tables for RESET# parameters and to
CE
CC3
) for read access when the device is in either
S29AL016M
and I
DC Characteristics
IH
RH
, but not within V
after the RESET# pin returns to V
CC4
represents the standby current
READY
IL
CC4
(not during Embedded
for at least a period of
CC
table represents the
). If RESET# is held
± 0.3 V, the device
Figure 14
ACC
IH
+
.
13