s29gl128n Meet Spansion Inc., s29gl128n Datasheet - Page 69

• Manufacturer Part Number: s29gl128n
• Description: 3.0 Volt-only Page Mode Flash Memory Featuring 110 Nm Mirrorbit ?rocess Technology
• Manufacturer: Meet Spansion Inc.

Write Operation Status
S29GL-N_00_B3 October 13, 2006
DQ7: Data# Polling
The device provides several bits to determine the status of a program or erase operation:
DQ2, DQ3, DQ5, DQ6, and DQ7.
the function of these bits. DQ7 and DQ6 each offer a method for determining whether a pro-
gram or erase operation is complete or in progress. The device also provides a
hardware-based output signal, RY/BY#, to determine whether an Embedded Program or
Erase operation is in progress or is completed.
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or
Erase algorithm is in progress or completed, or whether the device is in Erase Suspend. Data#
P olling is valid after the rising edge of the final WE# pulse in the command sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the
datum programmed to DQ7. This DQ7 status also applies to programming during Erase Sus-
pend. When the Embedded Program algorithm is complete, the device outputs the datum
programmed to DQ7. The system must provide the program address to read valid status in-
formation on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7
is active for approximately 1 µs, then the device returns to the read mode.
During the Embedded Erase algorithm, Data# Polling produces a 0 on DQ7. When the Em-
bedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data#
P olling produces a 1 on DQ7. The system must provide an address within any of the sectors
selected for erasure to read valid status information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected,
Data# Polling on DQ7 is active for approximately 100 µs, then the device returns to the read
mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the un-
protected sectors, and ignores the selected sectors that are protected. However, if the system
reads DQ7 at an address within a protected sector, the status may not be valid.
Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change
asynchronously with DQ0–DQ6 while Output Enable (OE#) is asserted low. That is, the device
may change from providing status information to valid data on DQ7. Depending on when the
system samples the DQ7 output, it may read the status or valid data. Even if the device has
completed the program or erase operation and DQ7 has valid data, the data outputs on DQ0–
DQ6 may be still invalid. Valid data on DQ0–DQ7 appears on successive read cycles.
T able 16 on page 72
the Data# Polling algorithm.
D a t a
shows the outputs for Data# Polling on DQ7.
S29GL-N MirrorBit™ Flash Family
Figure 14, on page 81
S h e e t
T able 16 on page 72
shows the Data# Polling timing diagram.
and the following subsections describe
Figure 5, on page 68
shows
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