nt1gc72b89a0nl Nanya Techology, nt1gc72b89a0nl Datasheet - Page 36

• Manufacturer Part Number: nt1gc72b89a0nl
• Description: Registered Ddr3 Sdram Dimm
• Manufacturer: Nanya Techology

NT1GC72B89A0NL / NT2GC72B8PA0NL
NT4GC72B4NA1NL / NT4GC72B8NA1NL / NT8GTC72B4NA1NL
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
AC Timing Specifications for DDR3 SDRAM Devices Used on Module
REV 1.1
06/2009
Clock Timing
Data Timing
Data Strobe Timing
tCK(DLL_OF Minimum Clock Cycle Time (DLL off mode)
tERR(10per) Cumulative error accross 10 cycles
tERR(11per) Cumulative error accross 11 cycles
tERR(12per) Cumulative error accross 12 cycles
tJIT(per,lck) Clock Period Jitter during DLL locking period
tERR(2per) Cumulative error accross 2 cycles
tERR(3per) Cumulative error accross 3 cycles
tERR(4per) Cumulative error accross 4cycles
tERR(5per) Cumulative error accross 5cycles
tERR(6per) Cumulative error accross 6 cycles
tERR(7per) Cumulative error accross 7 cycles
tERR(8per) Cumulative error accross 8 cycles
tERR(9per) Cumulative error accross 9 cycles
tERR(nper) Cumulative error accross n=13,14,..,49,50 cycles
tJIT(cc,lck)
tDS(base)
tDH(base)
tHZ(DQS)
tLZ(DQS)
tCK(avg)
tCH(avg)
tCK(abs)
tCH(abs)
tCL(avg)
tCL(abs)
tDQSCK
tHZ(DQ)
Symbol
JIT(per)
tLZ(DQ)
tJIT(cc)
tWPRE
tDQSQ
tWPST
tDQSH
tDQSS
tRPRE
tDQSL
tRPST
tQSH
tDSS
tDSH
tQSL
tQH
Average Clock Period(Refer to "Standard Speed
Average high pulse width
Average low pulse width
Absolute Clock Period
Absolute high pulse width
Absolute low pulse width
Clock Period Jitter
Cycle to Clcyle Period Jitter
Cycle to Cycle Period Jitter
DQS, DQS to DQ skew per group, per access
DQ output hold time from DQS, DQS
DQ low-impedence time from CK / 
DQ high-impedence time from CK / 
Data Setup time to DQS, DQS referenced to
Vih(ac)/ Vil(ac) levels
Data Hold time to DQS, DQS referenced to Vih(dc)/
Vil(dc) levels
DQS, DQS differential READ Preamble
DQS, DQS differential READ Postamble
DQS, DQS differential output high time
DQS, DQS differential output low time
DQS, DQS differential WRITE Preamble
DQS, DQS differential WRITE Postamble
DQS, DQS rising edge output access time from
rising CK, 
DQS, DQS low-impedance time (Referenced from
DQS, DQS high-impedance time (Referenced from
RL+BL/2)
DQS, DQS differential input low pulse width
DQS, DQS differential input high pulse width
DQS, DQS rising edge to CK,  rising edge
DQS, DQS falling edge setup time to CK,  rising
edge
DQS, DQS falling edge hold time to CK,  rising
Parameter
36
tCK(avg)min
tERR(npr)mi
tJIT(per)min
tJIT(per)min
0.68In(n)) *
n = (1+
-0.25
DDR3-1066 (-BE)
0.47
0.47
0.43
0.43
-132
-157
-175
-188
-200
-209
-217
-224
-231
-237
-242
0.38
-600
0.38
0.38
-300
-600
0.45
0.45
100
min
-90
-80
0.9
0.3
0.9
0.3
0.2
0.2
25
+
8
-
-
-
NANYA reserves the right to change products and specifications without notice.
180
160
tERR(npr)m
tCK(avg)ma
tJIT(per)ma
tJIT(per)ma
0.68In(n)) *
ax = (1+
0.53
0.53
0.55
0.55
0.25
max
132
157
175
188
200
209
217
224
231
237
242
150
300
300
300
300
300
x +
90
80
-
-
-
-
-
-
-
-
-
-
-
-
tCK(avg)min
tERR(npr)mi
tJIT(per)min
tJIT(per)min
0.68In(n)) *
n = (1+
© NANYA TECHNOLOGY CORPORATION
-0.25
DDR3-1333 (-CG)
-118
-140
-155
-168
-177
-186
-193
-200
-205
-210
-215
-500
-255
-500
0.47
0.47
0.43
0.43
0.38
0.45
0.45
min
-80
-70
0.9
0.3
0.4
0.4
0.9
0.3
0.2
0.2
30
65
8
+
-
-
-
160
140
tCK(avg)ma
tERR(npr)m
tJIT(per)ma
tJIT(per)ma
0.68In(n)) *
ax = (1+
max
0.53
0.53
0.55
0.55
0.25
118
140
155
168
177
186
193
200
205
210
215
125
250
250
255
250
250
x +
80
70
-
-
-
-
-
-
-
-
-
-
-
-
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
Unit
ns
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps