nt1gt72u89d0bd-ac Nanya Techology, nt1gt72u89d0bd-ac Datasheet - Page 24

• Manufacturer Part Number: nt1gt72u89d0bd-ac
• Description: 240pin Ddr2 Sdram Fully Buffered Dimm Based On 128mx8 1gb/2gb/4gb , 256mx4 4gb , And 512mx4 8gb Ddr2 Sdram
• Manufacturer: Nanya Techology

NT1GT72U89D0BD-AC / NT2GT72U8PD0BD-AC / NT4GT72U4ND0BD-AC / NT4GT72U8ND9BD-AC
NT1GT72U89D1BD-3C / NT2GT72U8PD1BD-3C / NT4GT72U4ND1BD-3C / NT8GTT72U4ND3YD-3C
NT1GT72U89D1BN-3C / NT2GT72U8PD1BN-3C / NT4GT72U4ND1BN-3C / NT8GTT72U4ND4YD-3C
NT1GT72U89D2BD-3C / NT2GT72U8PD2BD-3C / NT4GT72U4ND2BD-3C / NT8GTT72U4ND5YD-3C
NT1GT72U89D6BD-AC / NT2GT72U8PD6BD-AC / NT4GT72U8ND9BD-3C
AC Timing Specifications for DDR2 SDRAM Devices Used on Module
(T
REV 1.3
03/2009
CASE
= 0 °C ~ 85 ° C; V
t
Symbol
t
t
DQSL,(H)
t
LZ(DQS)
t
t
DQSCK
t
t
t
t
LZ(DQ)
t
t
DQSQ
t
t
WPST
WPRE
t
DQSS
t
t
RPRE
t
t
t
DIPW
RPST
Delay
MRD
t
t
QHS
t
DSH
REFI
RRD
t
t
t
t
t
IPW
t
DSS
RFC
QH
t
t
AC
CH
HP
CK
DH
DS
HZ
CL
IH
IS
DDQ
= 1.8V
DQ output access time from CK/
DQS output access time from CK/
CK high-level width
CK low-level width
Minimum half clk period for any given cycle;
defined by clk high (t
Clock Cycle Time
DQ and DM input hold time
DQ and DM input setup time
Input pulse width
DQ and DM input pulse width (each input)
Data-out high-impedance time from CK/
Data-out low-impedance time from CK/
DQS/
DQS-DQ skew (DQS & associated DQ signals)
Data hold Skew Factor
Data output hold time from DQS
Write command to 1st DQS latching transition
DQS input low (high) pulse width (write cycle)
DQS falling edge to CK setup time (write cycle)
DQS falling edge hold time from CK (write cycle)
Mode register set command cycle time
Write postamble
Write preamble
Address and control input hold time
Address and control input setup time
Read preamble
Read postamble
Minimum time clocks remains ON after CKE
asynchronously drops Low
Refresh to active/Refresh command time
Average Periodic Refresh Interval
(85º C < T
Average Periodic Refresh Interval
(0ºC = T
Active bank A to Active bank B command
CASE
0.1V; V
CASE
low-impedance time from CK/
= 85ºC)
= 95º C)
DD
Parameter
= 1.8V
CH
)
or clk low (t
0.1V, See AC Characteristics) (Part 1 of 2)
CL
) time
24
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
0.275
t
-0.45 +0.45 -0.40 +0.40
-0.25
Min.
0.48
0.48
0.35
0.35
0.40
0.35
t
-0.4
(t
2t
AC min
t
Min
175
100
t
t
CK
t
0.6
0.2
0.2
0.2
0.9
0.4
7.5
HP
min
QHS
IS
t
CL)
CH
3
2
-
-
-
IH
AC
+
+
127.5
-
,
-3C
3.9
7.8
t
t
t
Max.
+0.4
0.52
0.52
AC max
AC max
AC max
0.24
0.34
0.25
0.60
1.1
0.6
8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.250
0.175
-0.35 +0.35
t
-0.25
Min.
t
0.48
0.48
0.35
0.35
0.40
0.35
(t
125
2t
AC min
t
Min
t
t
2.5
0.6
0.2
0.2
0.9
0.4
CK
7.5
t
50
HP
QHS
min
IS
t
CL)
2
CH
-
-
-
IH
AC
+
+
127.5
-
,
-AC
3.9
7.8
t
t
t
Max.
0.52
0.52
0.20
0.30
0.25
0.60
AC max
AC max
AC max
1.1
0.6
8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Unit Notes
t
t
t
t
t
t
t
t
t
t
t
t
t
t
ns
ns
ns
ps
ps
ns
ns
ns
ns
ns
ns
ps
ps
ns
ns
>s
>s
ns
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
© NANYA TECHNOLOGY CORP.