nt1gt72u89d0bd-ac Nanya Techology, nt1gt72u89d0bd-ac Datasheet - Page 23

• Manufacturer Part Number: nt1gt72u89d0bd-ac
• Description: 240pin Ddr2 Sdram Fully Buffered Dimm Based On 128mx8 1gb/2gb/4gb , 256mx4 4gb , And 512mx4 8gb Ddr2 Sdram
• Manufacturer: Nanya Techology

NT1GT72U89D0BD-AC / NT2GT72U8PD0BD-AC / NT4GT72U4ND0BD-AC / NT4GT72U8ND9BD-AC
NT1GT72U89D1BD-3C / NT2GT72U8PD1BD-3C / NT4GT72U4ND1BD-3C / NT8GTT72U4ND3YD-3C
NT1GT72U89D1BN-3C / NT2GT72U8PD1BN-3C / NT4GT72U4ND1BN-3C / NT8GTT72U4ND4YD-3C
NT1GT72U89D2BD-3C / NT2GT72U8PD2BD-3C / NT4GT72U4ND2BD-3C / NT8GTT72U4ND5YD-3C
NT1GT72U89D6BD-AC / NT2GT72U8PD6BD-AC / NT4GT72U8ND9BD-3C
Operating, Standby, and Refresh Currents Definition table
REV 1.3
03/2009
Idd_Active_1
Icc_Active_1
Idd_Active_1
Icc_Active_1
Idd_Active_2
Icc_Active_2
Idd_Training
Icc_Training
Idd_Idle_0
Icc_Idle_0
Idd_Idle_1
Icc_Idle_1
Idd_Idle_2
Icc_Idle_2
NT8GTT72U4ND3YD-3C
NT8GTT72U4ND4YD-3C
NT4GT72U4ND0BD-AC
NT4GT72U8ND9BD-AC
NT1GT72U89D0BD-AC
NT1GT72U89D6BD-AC
NT2GT72U8PD0BD-AC
NT2GT72U8PD6BD-AC
NT2GT72U8PD1BD-3C
NT2GT72U8PD2BD-3C
NT2GT72U8PD1BN-3C
NT4GT72U4ND1BD-3C
NT4GT72U4ND2BD-3C
NT4GT72U4ND1BN-3C
NT4GT72U8ND9BD-3C
NT1GT72U89D1BD-3C
NT1GT72U89D2BD-3C
NT1GT72U89D1BN-3C
Symbol
(Write)
(Read)
Part Number
Idle Current, single or last DIMM. L0 state, idle (0BW). Primary channel enabled; Secondary Channel disabled. CKE
high. Command and address line stable. DRAM clock active.
Idle Current, first DIMM. L0 stage, idle (0BW). Primary and Secondary channels enabled. CKE high. Command and
address line stable. DRAM clock active.
Idle Current, DRAM power down. L0 stage, idle (0BW). Primary and Secondary channels enabled CKE low.
Command and address lines floated. DRAM clock active, ODT and CKE driven low.
Active Power. L0 state. 50% DRAM BW to downstream DIMM, 67% read, 33% write. Primary and Secondary
channels enabled. DRAM clock active, CKE high.
Active Power. L0 state. 50% DRAM BW to downstream DIMM, 100% read. Primary and Secondary channels
enabled. DRAM clock active, CKE high.
Active Power, data pass through. L0 state. 50% DRAM BW to downstream DIMM, 67% read, 33% write. Primary
and Secondary channels enabled. CKE high. Command and address lines stable. DRAM clock active.
Primary and Secondary channels enabled. 100% toggle on all channel lanes. DRAMs idle. 0BW. CKE high,
Command and address line stable. DRAM clock active.
0.96
0.96
0.91
0.77
0.77
1.34
1.34
1.30
1.16
1.10
2.28
2.09
2.04
1.93
3.60
3.60
Idd
˜ ` ˚ ˜ ` ˚ ˜ ` ˚ ¯ ` ¨ ¯ ˜ ` ˚ ¯ ` ¨ ˘ ˙ ` ˆ ¯ ¯ ` ¸ ¯ ˙ ` ˆ ˘ ¯ ` ¸ ¯ ˜ `
˜ ` ¸ ˜ ˜ ` ¨ ˜ ` ¸ ˘ ¯ ` ¯
Idle_0
3.39
3.39
2.86
1.85
2.64
3.34
3.34
2.51
1.89
2.67
2.85
2.86
1.90
2.70
2.96
2.96
Icc
0.97
0.97
0.91
0.77
0.77
1.35
1.35
1.30
1.16
1.11
2.31
2.11
2.04
1.93
3.67
3.67
Idd
Idle_1
4.16
4.16
2.92
2.37
3.87
4.04
4.04
3.55
2.40
3.93
4.03
3.63
2.42
4.10
3.74
3.74
Icc
0.97
0.97
0.88
0.79
0.77
1.35
1.35
1.31
1.18
1.11
2.32
2.15
2.10
2.50
3.70
3.70
Idd
˜ ` ¸ ˙ ¯ ` ¯
Idle_2
Parameter/Condition
4.16
4.16
3.76
2.37
3.87
4.05
4.05
3.72
2.42
3.94
4.02
3.74
2.44
4.22
3.78
3.78
23
Icc
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
0.99
0.99
0.92
0.77
0.94
1.43
1.43
1.30
1.16
1.25
2.39
2.23
2.11
2.51
3.78
3.78
Active_1 (W)
Idd
˙ ` ˆ ˜ ¯ ` ¨ ˜ ˙ ` ˆ ˜ ¯ ` ¨ ˜ ˜ ` ¸
4.18
4.18
3.75
2.35
4.20
4.20
4.20
3.72
2.42
4.18
4.27
3.76
2.45
4.24
3.80
3.80
Icc
0.99
0.99
0.94
0.77
0.99
1.33
1.33
1.30
1.16
1.25
2.41
2.21
2.11
2.51
3.76
3.76
Active_1 (R)
Idd
4.18
4.18
3.74
2.37
4.22
4.19
4.19
3.72
2.43
4.27
4.28
3.77
2.45
4.24
3.80
3.80
Icc
0.97
0.97
0.88
0.77
0.99
1.98
1.98
2.09
1.13
1.25
2.31
2.21
2.01
1.93
3.63
3.63
Idd
Active_2
© NANYA TECHNOLOGY CORP.
4.18
4.18
3.74
2.42
4.13
4.09
4.09
3.72
2.42
4.19
4.28
3.76
2.44
4.16
3.81
3.81
Icc
¯ ` ¨
¯ ` ˘ ˜ ` ¸ ˚ ¯ ` ¯ ˜ A
0.94
0.94
0.90
0.77
0.88
1.98
1.98
1.99
1.16
1.24
2.34
2.11
2.01
1.93
3.63
3.63
Idd
˜ ` ˚ ¯ ` ¨ ˜ A
Training
3.96
3.96
3.41
2.33
3.87
3.92
3.92
3.47
2.37
3.96
3.93
3.52
2.40
3.87
3.74
3.74
Icc
Unit
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A