ltc4350 Linear Technology Corporation, ltc4350 Datasheet - Page 9

• Manufacturer Part Number: ltc4350
• Description: Hot Swappable Load Share Controller
• Manufacturer: Linear Technology Corporation

APPLICATIO S I FOR ATIO
increases. The output voltage will then increase by an
amount equal to the voltage drop across R
external resistor, R
tionship in the I
as I
The maximum voltage that can be applied across R
1V. The range of the output voltage adjustment is set to be
V
voltage if the share bus is accidentally shorted to V
mentioned previously, this range is set to be 2% to 10%
in value.
The compensation elements, C
set the crossover frequencies of the two error amplifiers
E/A1 and E/A2. In the Design Example section, the
calculations for choosing all of the components will be
discussed.
Output Adjust Soft-Start
In the LTC4350, there is soft-start circuitry that holds the
COMP2 pin at ground until both the GATE pin is 4V above
the V
UV pin becoming active.
Upon power-up, most of the circuitry is active including
the circuits that monitor and adjust the output voltage.
The external power FETs are initially open circuit when
power is applied. It takes about 10ms to 100ms for the
FETs to transition from the off to the fully on state (as
discussed in the following Hot Swapping section). Dur-
ing this time the FB pin is near ground which forces the
SB to the positive rail. The COMP2 pin is then forced to
the positive rail, which forces the R
voltage at the output of the power supply is now adjusted
to its maximum adjusted value, which can be 10% above
nominal. Once the power FETs are turned on, the load will
see this adjusted output voltage. This appears to be a
voltage overshoot at the load that exists until the loop can
correct itself. The dominant pole in the loop exists on the
COMP2 pin. Therefore, the overshoot duration is deter-
mined by the discharge time of the COMP2 pin.
In order to eliminate this overshoot, the COMP2 pin is
clamped at ground until the GATE pin is 4V above the V
pin (power FETs are turned on). Now, the COMP2 pin will
begin to charge up until the FB pin regulates at 1.220V.
MAXADJ
ADJ
CC
= (V
pin and a timer cycle is completed following the
= R
COMP2
OUT
OUT
/R
– 0.58V)/R
SET
U
SET
block. The current in R
. This sets the worst-case output
, sets the voltage to current rela-
U
SET
CP1
.
W
and C
SET
CP2
pin to 1V. The
OUT
, are used to
U
is defined
OUT
CC
. The
SET
. As
CC
is
In cases where the power FETs are turned on but the
power supply is still ramping up, the load voltage may
overshoot. For these cases, the COMP2 pin is clamped to
ground during one timing cycle. If the UV pin is greater
than 1.244V, the chip begins the timer cycle. The timer
cycle uses a 2µA current source into an external capacitor
on the TIMER pin. As soon as the voltage at the TIMER pin
exceeds 1.220V, the timer cycle is over. The time-out is
defined as t = C
cycle, the power supply ramping should be complete.
Faults
There are several types of power supply output faults.
Shorts from the output to ground or to a positive voltage
greater than the normal output voltage are considered
“hard faults.” These faults require the bad power supply to
be immediately disconnected from the load in order to
prevent disruption of the system. “Soft faults” include
power supply failed open-circuit or load current sharing
failure where the output voltage is normal but load sharing
between several supplies is not equal. The LTC4350 can
isolate soft and hard faults and signal a system controller
using the STATUS pin.
HARD FAULTS
The LTC4350 can identify faults in the power supply and
isolate them from the load if optional external power FETs
are included between the power supply and the load. In the
case of a power supply output short to ground, the reverse
current block will sense that the voltage across the current
sense resistor has changed directions and has exceeded
30mV for more than 5µs. The gate of the external power
FETs is immediately pulled low disconnecting the short
from the load. The gate is allowed to ramp-up and turn-on
the power FETs as soon as the reverse voltage across the
sense resistor is less than 30mV.
The condition where a power supply output shorts to a
high voltage is referred to as an overvoltage fault. In this
case, the gate of the power FETs is pulled low disconnect-
ing the overvoltage from the load. This feature uses the OV
pin to monitor the power supply output voltage. Once the
voltage on the OV pin exceeds the 1.220V threshold, the
gate of the external power FETs is pulled low.
T
• 1.220V/2µA. At the end of the timer
LTC4350
4350fa
9