ltc4259a-1 Linear Technology Corporation, ltc4259a-1 Datasheet - Page 17

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ltc4259a-1

Manufacturer Part Number
ltc4259a-1
Description
Quad Ieee 802.3af Power Over Ethernet Controller With Ac Disconnect
Manufacturer
Linear Technology Corporation
Datasheet
APPLICATIO S I FOR ATIO
listed in Table 2. During classification, the LTC4259A-1
controls and measures the port voltage through the
DETECT n pin. Note that class 4 is presently specified by the
IEEE as reserved for future use. Figure 14 shows a PD load
line, starting with the shallow slope of the 25k signature re-
sistor below 10V, then drawing the classification current
(in this case, class 3) between 14.5V and 20.5V. The
LTC4259A-1’s load line for classification is also shown in
Figure 14. It has low impedance until current limit is reached
at 55mA (min).
The LTC4259A-1 will classify a port immediately after a
successful detection cycle in Semiauto or Auto modes, or
when commanded to in Manual mode. It measures the PD
classification signature current by applying 18V (typ) to
the port and measuring the resulting current. It reports the
detected class in the Class Status bits in the correspond-
ing Port Status register. Note that in Auto mode, the port
will power up regardless of which class is detected.
The classification circuitry is disabled when the port is in
Shutdown mode, powered up, or the corresponding Class
Enable bit is cleared.
POWER CONTROL
The primary function of the LTC4259A-1 is to control the
delivery of power to the PSE port. It does this by control-
ling the gate drive voltage of an external power MOSFET
while monitoring the current via a sense resistor and the
output voltage at the OUT pin. This circuitry serves to
couple the raw isolated –48V input supply to the port in a
60
50
40
30
20
10
0
0
Figure 14. PD Classification
5
U
PD LOAD
TYPICAL
CLASS 3
VOLTAGE (V
LINE
10
U
CURRENT
CLASS 4
CLASS 3
OVER
CLASS 2
CLASS 1
CLASS 0
CLASS
15
)
PSE LOAD LINE
W
48mA
33mA
20
23mA
14.5mA
6.5mA
4259A F14
25
U
controlled manner that satisfies the PD’s power needs
while minimizing disturbances on the –48V backplane.
Gate Currents
Once the decision has been made to turn on power to a
port, the LTC4259A-1 uses a 50µA current source to pull
up on the GATE pin. Under normal power-up circum-
stances, the MOSFET gate will charge up rapidly to V
MOSFET threshold voltage), the MOSFET current will rise
quickly to the current limit level and the GATE pin will be
servoed to maintain the proper I
When output charging is complete, the MOSFET current
will fall and the GATE pin will be allowed to continue rising
to fully enhance the MOSFET and minimize its on resis-
tance. The final V
turned off, a 50µA current source pulls down on the GATE
pin, turning the MOSFET off in a controlled manner.
No External Capacitors
No external capacitors are required on the GATE pins for
active current limit stability, lowering part count and cost.
This also allows the fastest possible turn-off under severe
overcurrent conditions, providing maximum safety and
protection for the MOSFETs, load devices and board traces.
Connecting capacitors to the external MOSFET gates can
adversely affect the LTC4259A-1’s ability to respond to a
shorted port.
Inrush Control
The 802.3af standard lists two separate maximum current
limits, I
ues, the LTC4259A-1 implements both as a single current
limit using V
differentiated through the use of t
tively (see t
maintain consistency with the standard, the I
is used when referring to an initial t
When the LTC4259A-1 turns on a port, it turns on the
MOSFET by pulling up on the gate. The LTC4259A-1 is
designed to power up the port in current limit, limiting the
inrush current to I
The port voltage will quickly rise to the point where the PD
reaches its input turn-on threshold and begins to draw
LIM
and I
ICUT
LIM
Timing and t
INRUSH
(described below). Their functions are
INRUSH
GS
is nominally 13V. When a port is
. Because they have identical val-
.
START
LTC4259A-1
INRUSH
ICUT
START
Timing sections). To
and t
charging current.
power-up event.
START
INRUSH
, respec-
17
4259a1fa
T
term
(the

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