ltc4259a-1 Linear Technology Corporation, ltc4259a-1 Datasheet
ltc4259a-1
Related parts for ltc4259a-1
ltc4259a-1 Summary of contents
Page 1
... Powered Device (PD) detection and classification ca- pability, and programmable PD disconnect using sensing. Used with power MOSFETs and passives as in Figure 1, the LTC4259A-1 can implement a complete IEEE 802.3af-compliant PSE. 2 The LTC4259A-1 can operate autonomously or be controlled ...
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... LTC4259A ABSOLUTE AXI U RATI GS (Note 1) Supply Voltages V to DGND .......................................... – 0. AGND ......................................... 0.3V to – 70V EE DGND to AGND (Note 2) .................................... ±1V Digital Pins SCL, SDAIN, SDAOUT, INT, AUTO, RESET SHDN ................. DGND – 0.3V to DGND + 5V Analog Pins GATE n (Note 3) ................... V EE DETECT n Peak Currents (Note 4) .................. ±80mA SENSE n ...
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... Time to Measure PD Signature Resistance (Figure 2) From Successful Detect in Auto or Semiauto Mode to Class Complete From Classify Command in Manual Mode (Figure 2) (Figure 2) From Valid Detect to Port On in Auto Mode (Figure 2) From Port On Command to GATE Pin Current = I (Note 10) LTC4259A-1 = 3.3V –48V unless otherwise noted DD EE MIN TYP MAX ● ...
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... Note 6: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground (AGND and DGND) unless otherwise specified. Note 7: The LTC4259A-1 is designed to maintain a port voltage of –46.6V to –57V. The V diode, MOSFET and sense resistor. ...
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... PORT VOLTAGE WITH TYPICAL CMPD3003 –16 –18 PIN VOLTAGE – CLASSIFICATION CURRENT (mA) 4258 G05 LTC4259A-1 Powering On a 180µF Load –48V GND EE PORT GATE +14V FET ON LOAD FULLY V EE ...
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... LTC4259A TEST PORT GATE n INT Figure 2. Detect, Class and Turn-On Timing in Auto or Semiauto Modes V SENSE n V SENSE n V MIN INT t VMIN Figure 4. DC Disconnect Timing SCL t 2 SDA INSERTED t DET V CLASS EE t CLSDLY t t DETDLY ...
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... Figure 9. Reading the Interrupt Register (Short Form R/W ACK AD3 ACK BY SLAVE FRAME 1 FRAME 2 ALERT RESPONSE ADDRESS BYTE SERIAL BUS ADDRESS BYTE Figure 10. Reading from Alert Response Address LTC4259A ACK ACK BY STOP BY SLAVE MASTER FRAME 3 DATA BYTE 4259A F07 R/W ACK D7 ...
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... CTIO S RESET (Pin 1): Chip Reset, Active Low. When the RESET pin is low, the LTC4259A-1 is held inactive with all ports off and all internal registers reset to their power-up states. When RESET is pulled high, the LTC4259A-1 begins normal operation. RESET can be connected to an external capacitor or RC network to provide a power turn-on delay ...
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... GATE1 (Pin 33): Port 1 Gate Drive. See GATE 4. OUT1 (Pin 34): Port 1 Output Voltage Monitor. See OUT4. AUTO (Pin 35): Auto Mode Input. Auto mode allows the LTC4259A-1 to detect and power even if there is no host controller present on the I the AUTO pin determines the state of the internal registers when the LTC4259A-1 is reset or comes out of V (see the Register map in Table 1) ...
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... LTC4259A-1 W TABLE 1. REGISTER AP 10 4259a1fa ...
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... In Manual mode, this register indicates that the requested detection/classification cycle has completed and LTC4259A-1 the LTC4259A-1 is awaiting further instructions. In Semiauto or Auto modes, these bits indicate that the De- tect Status and Class Status bits in the Port Status regis- ters are valid. The Detect Event bits latch high and will remain high until cleared by reading from address 05h ...
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... Operating Mode (Address 12h): Operating Mode Configu- ration, Read/Write. This register contains the mode bits for each of the four ports in the LTC4259A-1. See Table 1 for mode bit encoding. At power-up, all bits in this register will be set to the logic state of the AUTO pin (Pin 35). See Operating Modes in the Applications Information section ...
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... OSCIN pin from setting the Osc Fail bit and causing a Supply Event Interrupt. Setting bit 7 enables the INT pin. If this bit is reset, the LTC4259A-1 will not pull down the INT pin in any condition nor will it respond to the Alert Re- sponse Address. This bit is set by default. ...
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... LTC4259A REGISTER FU CTIO S way, the condition causing the LTC4259A-1 to pull the INT pin down must be removed before the LTC4259A-1 will be able to pull INT down again. This can be done by reading and clearing the event registers or by writing a 1 into bit ...
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... Power Off bit in the Power Enable PB register. Power-On RESET At turn-on or any time the LTC4259A-1 is reset (either by pulling the RESET pin low or writing to the global Reset All bit), all the ports turn off and all internal registers predefined state, shown in Table 1 ...
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... W U The LTC4259A-1 will not report Detect Good if the PD has more than 5µF in parallel with its signature resistor. The port’s operating mode controls if and when the LTC4259A-1 runs a detection cycle. In manual mode, the port will sit idle until a Restart Detection (register 18h) command is received ...
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... I is used when referring to an initial t When the LTC4259A-1 turns on a port, it turns on the MOSFET by pulling up on the gate. The LTC4259A-1 is designed to power up the port in current limit, limiting the inrush current to I ...
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... Dual-Level Current Limit permitted to draw up to 15.4W continuously and up to 400mA for 50ms. The LTC4259A-1 has two corre- sponding current limit thresholds (425mA typ). These are given by the equations: ...
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... With 0.5Ω sense resistors, this limits the short-circuit current to 60mA (typ) instead of the full 425mA (typ) current limit. When the LTC4259A foldback, the t timer is active. ICUT ...
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... LTC4259A-1 to normal operating mode. A substantial transient surge suppressor can typically protect the LTC4259A-1 and the rest of the PSE from these faults. Placing a polyfuse between the RJ-45 connector and the LTC4259A-1 and its associated circuitry can pro- vide additional protection. To meet safety requirements, place the polyfuse in the ground leg of the PSE’ ...
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... PORT OFF IN t DIS sence of a PD. Consequently, in the same application SHORT EFFECT circuit the LTC4259A-1 will have less sensitivity to parasitics CIRCUIT 4259A F17 like leakage and stray capacitance than an LTC4259A. Both the LTC4259A and LTC4259A-1 (used with the recommended application circuit) meet all the AC discon- nect requirements of 802 ...
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... In of 0.1µF. On the PSE order to produce the desired capacitance at the operating bias, 100V or 250V X7R capacitors should be used with ≈ 100Hz, use at least the LTC4259A- PSE DET As illustrated in Figure 19, the Power over Ethernet con- nection between the PSE and PD includes a large amount of capacitance ...
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... PD has just been removed. When the PD is still connected there will be almost no AC signal at the port. The LTC4259A-1 monitors Pin 36 for the presence of an oscillating signal signal is present and the Osc Fail Mask bit is set, then Osc Fail (bit 1 of the Supply Event register) is set, triggering an interrupt. As the LTC4259A- 1’ ...
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... AC disconnect enabled (and DC dis- connect not enabled) will automatically disconnect. After the LTC4259A-1 is reset (by power on, Reset All bit or the RESET pin) the Osc Fail bit is set. Once the Osc Fail bit is cleared, it will only be set by an invalid signal on the OSCIN pin or another reset ...
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... SDAOUT AD0 LTC4259A-1 AD1 AD2 AD3 DGND AGND BYP 0.1µF • 0.1µF • • INT SCL SDAIN SDAOUT AD0 LTC4259A-1 AD1 AD2 AD3 DGND AGND BYP 0.1µF 0.1µ INT SCL SDAIN SDAOUT AD0 LTC4259A-1 AD1 AD2 AD3 DGND AGND BYP 0.1µ ...
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... The master initiates the ARA procedure with a START condition and the 7-bit ARA bus address (0001100)b followed by the Read Bit (Rd LTC4259A-1 is asserting the INT pin, it acknowledges and sends its 7-bit bus address (010A While it is sending its address, it monitors the SDAIN pin ...
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... Clear Interrupt pin bit (bit 6 of register 1Ah), the condition causing the LTC4259A-1 to pull the INT pin down must be removed before the LTC4259A-1 will be able to pull INT down again. This can be done by reading and clearing the event registers or by writing a 1 into the Clear All Interrupts bit (bit 7 of register 1Ah) ...
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... For further assistance please contact Lin- ear Technology’s Applications department. ® 1619 to control Sense Resistors The LTC4259A-1 is designed to use a 0.5Ω sense resistor monitor the current through each port. The value of S the sense resistor has been minimized in order to reduce power loss and as a consequence, the voltage which the LTC4259A-1 must measure is small ...
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... CUT MIN ance, use a resistor with 0.5% or better accuracy. Power MOSFETs The LTC4259A-1 controls power MOSFETs in order to regulate current flow through the Ethernet ports. Under certain conditions these MOSFETs have to dissipate sig- nificant power. See the Choosing External MOSFETs sec- tion for a detailed discussion of the requirements these devices must meet ...
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... OSCIN pin. Requirements for this signal are pro- vided in the OSCIN Input and Oscillator Requirements section. Out-of-band noise on the OSCIN pin will disrupt the LTC4259A-1’s ability to sense the absence of a PD. Any noise present at the OSCIN pin is amplified by the DD LTC4259A-1 and driven out of the DETECT pins (of pow- ered ports with AC disconnect enabled) ...
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... DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.152mm (0.006") PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE LTC4259A-1 15.291 – 15.545* (.602 – .612) 10.11 – 10.55 (.398 – .415) 2.286 – ...
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... Linear Technology Corporation 32 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 ● ISOLATED 3.3V 0.1µF OSCIN DGND AGND SCL 1/4 SDAIN LTC4259A-1 SDAOUT INT V SENSE GATE OUT EE 2k 0.1µ 0.5Ω Q1 –48V IRFM120A ISOLATED U3 200Ω 200Ω PHY ...