ltc3787gn Linear Technology Corporation, ltc3787gn Datasheet - Page 25

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ltc3787gn

Manufacturer Part Number
ltc3787gn
Description
Ltc3787 - Polyphase Synchronous Boost Controller
Manufacturer
Linear Technology Corporation
Datasheet

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LTC3787GN
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Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V
amount equal to ΔI
series resistance of C
discharge C
forces the regulator to adapt to the current change and
return V
time V
ringing, which would indicate a stability problem. OPTI-
LOOP compensation allows the transient response to be
optimized over a wide range of output capacitance and
ESR values. The availability of the ITH pin not only allows
optimization of control loop behavior, but it also provides
a DC coupled and AC filtered closed loop response test
point. The DC step, rise time and settling at this test
point truly reflects the closed loop response. Assuming a
predominantly second order system, phase margin and/
or damping factor can be estimated using the percentage
of overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin. The ITH
external components shown in the Figure 10 circuit will
provide an adequate starting point for most applications.
The ITH series R
loop compensation. The values can be modified slightly
to optimize transient response once the final PC layout
is complete and the particular output capacitor type and
value have been determined. The output capacitors must
be selected because the various types and values determine
the loop gain and phase. An output current pulse of 20%
to 80% of full-load current having a rise time of 1μs to
10μs will produce output voltage and ITH pin waveforms
that will give a sense of the overall loop stability without
breaking the feedback loop.
Placing a power MOSFET and load resistor directly across
the output capacitor and driving the gate with an ap-
propriate signal generator is a practical way to produce
a realistic load step condition. The initial output voltage
step resulting from the step change in output current may
not be within the bandwidth of the feedback loop, so this
signal cannot be used to determine phase margin. This
applicaTions inForMaTion
OUT
OUT
can be monitored for excessive overshoot or
OUT
to its steady-state value. During this recovery
generating the feedback error signal that
C
-C
LOAD(ESR)
C
OUT
filter sets the dominant pole-zero
. ΔI
LOAD
, where ESR is the effective
also begins to charge or
OUT
shifts by an
is why it is better to look at the ITH pin signal which is
in the feedback loop and is the filtered and compensated
control loop response.
The gain of the loop will be increased by increasing R
and the bandwidth of the loop will be increased by de-
creasing C
is decreased, the zero frequency will be kept the same,
thereby keeping the phase shift the same in the most
critical frequency range of the feedback loop. The output
voltage settling behavior is related to the stability of the
closed-loop system and will demonstrate the actual overall
supply performance.
A second, more severe transient is caused by switching
in loads with large (>1μF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
C
should be controlled so that the load rise time is limited to
approximately 25 • C
require a 250μs rise time, limiting the charging current
to about 200mA.
Design Example
As a design example, assume V
V
75mV, and f = 350kHz.
The components are designed based on single channel
operation. The inductance value is chosen first based on
a 30% ripple current assumption. Tie the PLLIN/MODE
pin to GND, generating 350kHz operation. The minimum
inductance for 30% ripple current is:
The largest ripple happens when V
where the average maximum inductor current for each
channel is:
LOAD
IN
I
∆I
MAX
= 22V (max), V
L
OUT
to C
=
=
f • L
V
, causing a rapid drop in V
C
IN
OUT
I
. If RC is increased by the same factor that C
OUT(MAX)
 
1−
is greater than 1:50, the switch rise time
2
OUT
V
V
OUT
IN
LOAD
 •
= 24V, I
 
 
. Thus, a 10μF capacitor would
V
V
OUT
IN
OUT(MAX)
 
= 8A
IN
OUT
IN
= 8A, V
= 12V (nominal),
= 1/2V
. No regulator can
LTC3787
SENSE(MAX)
OUT
25
= 12V,
3787fa
=
C
C

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