ltc3869gn-2 Linear Technology Corporation, ltc3869gn-2 Datasheet - Page 23

• Manufacturer Part Number: ltc3869gn-2
• Description: Ltc3869/ltc3869-2 - Dual, 2-phase Synchronous Step-down Dc/dc Controllers
• Manufacturer: Linear Technology Corporation

APPLICATIONS INFORMATION
Phase-Locked Loop and Frequency Synchronization
The LTC3869 has a phase-locked loop (PLL) comprised of
an internal voltage-controlled oscillator (V
detector. This allows the turn-on of the top MOSFET of
controller 1 to be locked to the rising edge of an external
clock signal applied to the MODE/PLLIN pin. The turn-on
of controller 2’s top MOSFET is thus 180 degrees out-
of-phase with the external clock. The phase detector is
an edge sensitive digital type that provides zero degrees
phase shift between the external and internal oscillators.
This type of phase detector does not exhibit false lock to
harmonics of the external clock.
The output of the phase detector is a pair of complementary
current sources that charge or discharge the internal filter
network. There is a precision 10µA of current flowing out
of FREQ pin. This allows the user to use a single resistor
to SGND to set the switching frequency when no external
clock is applied to the MODE/PLLIN pin. The internal switch
between FREQ pin and the integrated PLL filter network
is ON, allowing the filter network to be pre-charged to the
same voltage potential as the FREQ pin. The relationship
between the voltage on the FREQ pin and the operating
frequency is shown in Figure 9 and specified in the Electri-
cal Characteristics table. If an external clock is detected on
the MODE/PLLIN pin, the internal switch mentioned above
will turn off and isolate the influence of FREQ pin. Note
that the LTC3869 can only be synchronized to an external
clock whose frequency is within range of the LTC3869’s
internal V
780kHz. A simplified block diagram is shown in Figure 10.
If the external clock frequency is greater than the internal
oscillator’s frequency, f
tinuously from the phase detector output, pulling up the
filter network. When the external clock frequency is less
than f
the filter network. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. The voltage on the filter network is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
the filter capacitor holds the voltage.
OSC
CO
, current is sunk continuously, pulling down
. This is guaranteed to be between 250kHz and
OSC
, then current is sourced con-
CO
) and a phase
Typically, the external clock (on MODE/PLLIN pin)
input high threshold is 1.6V, while the input low threshold
is 1V. It is not recommended to apply the external clock
when IC is in shutdown.
Minimum On-Time Considerations
Minimum on-time t
that the LTC3869 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that
OSCILLATOR
t
EXTERNAL
ON(MIN)
Figure 10. Phase-Locked Loop Block Diagram
900
800
700
600
500
400
300
200
100
Figure 9. Relationship Between Oscillator
Frequency and Voltage at the FREQ Pin
0
<
MODE/
PLLIN
0
V
V
IN
OUT
LTC3869/LTC3869-2
(ƒ)
0.5
FREQUENCY
ON(MIN)
DETECTOR
FREQ PIN VOLTAGE (V)
DIGITAL
PHASE/
1
is the smallest time duration
SYNC
1.5
2.4V 5V
2
3869 F09
10µA
2.5
FREQ
R
23
SET
VCO
3869 F10
3869f