ltc3834-1 Linear Technology Corporation, ltc3834-1 Datasheet

Page 1

... OPTI-LOOP compen- sation allows the transient response to be optimized over a wide range of output capacitance and ESR values. The LTC3834-1 features a precision 0.8V reference . The 4V to 36V input supply range encompasses a wide range of bat- tery chemistries. The TRACK/SS pin ramps the output voltage during start- up ...

Page 2

... LTC3834 ABSOLUTE AXI U RATI GS (Note 1) Input Supply Voltage (V ).........................36V to – 0.3V IN Top Side Driver Voltage (BOOST) ..............42V to – 0.3V Switch Voltage (SW) ....................................36V to – 5V INTV (BOOST-SW).................................8.5V to – 0.3V CC, RUN, TRACK/SS ......................................... 7V to – 0.3V + – SENSE , SENSE Voltages .........................11V to – 0.3V PLLIN/MODE, PLLLPF ......................... INTV I V Voltages .......................................2.7V to – 0.3V ...

Page 3

... PLLIN/MODE OSC Note 4: The LTC3834-1 is tested in a feedback loop that servos V specified voltage and measures the resultant V Note 5: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. See Applications Information. Note 6: Rise and fall times are measured using 10% and 90% levels. Delay times are measured using 50% levels ...

Page 4

... LTC3834 TYPICAL PERFOR A CE CHARACTERISTICS Efficiency and Power Loss vs Output Current 100 Burst Mode OPERATION FORCED CONTINUOUS MODE 90 PULSE SKIPPING MODE 12V 3.3V 70 OUT FIGURE 10 CIRCUIT 0 0.000001 0.0001 0.01 1 OUTPUT CURRENT (A) 38341 G01 Load Step (Burst Mode Operation) ...

Page 5

... V COMMON MODE VOLTAGE (V) SENSE Quiescent Current vs Temperature 0.6 0.7 0.8 0.9 –45 38341 G16 LTC3834 25ºC, unless otherwise noted. A INTV Line Regulation CC 5.5 5.4 5.3 5.2 5.1 5 INPUT VOLTAGE (V) 38341 G11 Maximum Current Sense Threshold vs Duty 120 ...

Page 6

... LTC3834 TYPICAL PERFOR A CE CHARACTERISTICS SENSE Pins Total Input Bias Current 1.0 0 0.2 0.4 0.6 0.8 1.2 I VOLTAGE (V) TH 38341 G18 Regulated Feedback Voltage vs Temperature 808 806 804 802 800 798 796 794 792 –45 –30 – TEMPERATURE (°C) ...

Page 7

... SS pin. A internal 1μA pull-up current source is connected to this pin. A capacitor to ground at this pin sets the ramp time to final regulated output voltage. Alternatively, a resistor divider on another voltage supply connected to this pin allows the LTC3834-1 output to track the other supply during startup. V (Pin 4/Pin 4): Receives the remotely sensed feed- ...

Page 8

... In this case, an R-C filter must be connected to the PLLLPF pin. When not synchronizing to an external clock, this input determines how the LTC3834-1 operates at light loads. Pulling this pin below 0.7V selects Burst Mode operation. Tying this pin to INTV ...

Page 9

... C to recharge. Shutdown and Start-Up (RUN and TRACK/SS Pins) The LTC3834-1 can be shut down using the RUN pin. Pulling this pin below 0.7V shuts down the main control loop for the controller. A low disables the controller and most internal circuits, including the INTV at which time the LTC3834-1 draws only 4μ ...

Page 10

... INTV , or tied to SGND to select 400kHz, 530kHz 250kHz, respectively. A phase-locked loop (PLL) is available on the LTC3834-1 to synchronize the internal oscillator to an external clock source that is connected to the PLLIN/MODE pin. In this case, a series R-C should be connected between the PLLLPF pin and SGND to serve as the PLL’s loop filter. The ...

Page 11

... The typical capture range of the LTC3834-1’s phase- locked loop is from approximately 115kHz to 800kHz, with a guarantee to be between 140kHz and 650kHz. In other words, the LTC3834-1’s PLL is guaranteed to lock to an external clock source whose frequency is between 140kHz and 650kHz. The typical input clock thresholds on the PLLIN/MODE pin are 1 ...

Page 12

... Selection Two external power MOSFETs must be selected for each ). The maximum I L controller in the LTC3834-1: One N-channel MOSFET for the top (main) switch, and one N-channel MOSFET for the bottom (synchronous) switch. The peak-to-peak drive levels are set by the INTV voltage ...

Page 13

... DS(ON) design. Due to the high operating frequency of the LTC3834-1, ceramic capacitors can also be used for C Always consult the manufacturer if there is any question. The selection of C resistance (ESR). Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering. The output ripple ( V Δ ...

Page 14

... LTC3834 APPLICATIO S I FOR ATIO Setting Output Voltage The LTC3834-1 output voltage is set by an external feed- back resistor divider carefully placed across the output, as shown in Figure 1. The regulated output voltage is deter- mined by: ⎛ ⎞ ⎜ ⎟ • ...

Page 15

... TRACK/ X INTV pin from the V CC gate drivers and much of the LTC3834-1’s internal cir- cuitry. The V to 5.25V. It can supply a peak current of 50mA and must be bypassed to ground with a minimum of 4.7μF ceramic R TRACKB capacitor ...

Page 16

... W U Fault Conditions: Current Limit and Current Foldback The LTC3834-1 includes current foldback to help limit load current when the output is shorted to ground. If the output falls below 70% of its nominal output level, then the LDO. IN maximum sense voltage is progressively lowered from • ...

Page 17

... MODE, is shown in Figure 6 and specified in the Electrical Characteristics table. Note that the LTC3834-1 can only be synchronized to an external clock whose frequency is within range of the LTC3834-1’s internal VCO, which is nominally 115kHz to 800kHz. This is guaranteed to be between 140kHz and 650kHz. A simplified block diagram is shown in Figure 7 ...

Page 18

... W U Minimum On-Time Considerations Minimum on-time t that the LTC3834-1 is capable of turning on the top MOSFET determined by internal timing delays and the gate charge required to turn on the top MOSFET. Low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that ...

Page 19

... ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC3834-1 circuits regulator current losses, 4) Topside MOSFET transition losses. ...

Page 20

... LTC3834 APPLICATIO S I FOR ATIO Checking Transient Response The regulator loop response can be checked by looking at the load current transient response. Switching regulators take several cycles to respond to a step in DC (resistive) load current. When a load step occurs, V amount equal to I (ESR), where ESR is the effective ...

Page 21

... RMS current rating of at least temperature assuming only this channel is on. C chosen with an ESR of 0.02 for low output ripple. The output ripple in continuous mode will be highest at the maximum input voltage. The output voltage ripple due to ESR is approximately: V ORIPPLE MILLER LTC3834 ° ...

Page 22

... All of these nodes have very large and fast moving signals and therefore should be kept on the “output side” of the LTC3834-1 and occupy minimum PC trace area. 7. Use a modified “star ground” technique: a low imped- ...

Page 23

... Compensation of the voltage loop will be much more sensitive to component selection. This behavior can be investigated by tempo- while moni- IN rarily shorting out the current sensing resistor—don’t worry, the regulator will still maintain control of the output voltage. LTC3834 SENSE OUT C R OUT ...

Page 24

... INTV CC 4.7μF PLLIN/MODE – SENSE + SENSE PGND High Efficiency 12V to 1.8V, 2A Step-Down Converter PLLLPF RUN C B 0.22μF TRACK/SS BOOST LTC3834-1 100pF SGND INTV CC 4.7μF PLLIN/MODE – SENSE + SENSE PGND 10V TO 36V IN M1 10μF L1 7.2μH 0.015Ω V OUT 9 ...

Page 25

... PLLLPF RUN C B 0.22μF TRACK/SS BOOST LTC3834-1 100pF SGND INTV CC 4.7μF PLLIN/MODE – SENSE + SENSE PGND LTC3834 5. 10μF 36V L1 3.3μH 0.012Ω V OUT OUT 150μF M2 38341 TA04 10μF 36V L1 2.2μ ...

Page 26

... LTC3834-1 PACKAGE DESCRIPTIO 3.50 ±0.05 1.65 ±0.05 2.20 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS PIN 1 TOP MARK (SEE NOTE 6) 0.200 REF NOTE: 1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC PACKAGE OUTLINE MO-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH ...

Page 27

... Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. LTC3834-1 .189 – .196* (4.801 – 4.978) ...

Page 28

... Linear Technology Corporation. PolyPhase is a registered trademark of Linear Technology Corporation. Pentium is a registered trademark of Intel Corporation. SENSE Linear Technology Corporation 28 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 ● PLLLPF RUN C B 0.22μF TRACK/SS BOOST LTC3834 150pF CMDSH-3 SGND INTV CC 4.7μF PLLIN/MODE – SENSE + SENSE PGND COMMENTS Up to 97% Efficiency ...