ltc2182 Linear Technology Corporation, ltc2182 Datasheet - Page 28

• Manufacturer Part Number: ltc2182
• Description: 16-bit, 65msps/ 40msps/25msps Low Power Dual Adcs
• Manufacturer: Linear Technology Corporation

APPLICATIONS INFORMATION
LTC2182/LTC2181/LTC2180
Table 3. Serial Programming Mode Register Map (PAR/SER = GND)
REGISTER A0: RESET REGISTER (ADDRESS 00h)
REGISTER A1: POWER-DOWN REGISTER (ADDRESS 01h)
REGISTER A2: TIMING REGISTER (ADDRESS 02h)
28
Bit 7
Bits 6-0
Bits 7-2
Bits 1-0
Bits 7-4
Bit 3
Bits 2-1
Bit 0
RESET
D7
D7
D7
X
X
RESET
0 = Not Used
1 = Software Reset. All Mode Control Registers Are Reset to 00h. The ADC Is Momentarily Placed in SLEEP Mode. This Bit Is
Automatically Set Back to Zero at the End of the SPI Write Command. The Reset Register Is Write-Only. Data Read Back from the
Reset Registar Will Be Random.
Unused, Don’t Care Bits.
Unused, Don’t Care Bits.
PWROFF1:PWROFF0
00 = Normal Operation
01 = Channel 1 in Normal Operation, Channel 2 in Nap Mode
10 = Channel 1 and Channel 2 in Nap Mode
11 = Sleep Mode
Unused, Don’t Care Bits.
CLKINV
0 = Normal CLKOUT Polarity (As Shown in the Timing Diagrams)
1 = Inverted CLKOUT Polarity
CLKPHASE1:CLKPHASE0
00 = No CLKOUT Delay (As Shown in the Timing Diagrams)
01 = CLKOUT
10 = CLKOUT
11 = CLKOUT
Note: If the CLKOUT Phase Delay Feature Is Used, the Clock Duty Cycle Stabilizer Must Also Be Turned On
DCS
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
D6
D6
D6
X
X
X
+
+
+
/CLKOUT
/CLKOUT
/CLKOUT
Output Clock Invert Bit
Clock Duty Cycle Stabilizer Bit
Software Reset Bit
–
–
–
Delayed by 45° (Clock Period • 1/8)
Delayed by 90° (Clock Period • 1/4)
Delayed by 135° (Clock Period • 3/8)
D5
D5
D5
X
X
X
Power Down Control Bits
Output Clock Phase Delay Bits
D4
D4
D4
X
X
X
CLKINV
D3
D3
D3
X
X
CLKPHASE1
D2
D2
D2
X
X
CLKPHASE0
PWROFF1
D1
D1
D1
X
PWROFF0
DCS
D0
D0
D0
X
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