ltc2182 Linear Technology Corporation, ltc2182 Datasheet

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ltc2182

Manufacturer Part Number
ltc2182
Description
16-bit, 65msps/ 40msps/25msps Low Power Dual Adcs
Manufacturer
Linear Technology Corporation
Datasheet

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FEATURES
APPLICATIONS
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TYPICAL APPLICATION
ANALOG
ANALOG
65MHz
CLOCK
INPUT
INPUT
CH 1
CH 2
Two-Channel Simultaneously Sampling ADC
77dB SNR
90dB SFDR
Low Power: 160mW/115mW/78mW Total
80mW/58mW/39mW per Channel
Single 1.8V Supply
CMOS, DDR CMOS, or DDR LVDS Outputs
Selectable Input Ranges: 1V
550MHz Full Power Bandwidth S/H
Optional Data Output Randomizer
Optional Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Serial SPI Port for Configuration
64-Pin (9mm × 9mm) QFN Package
Communications
Cellular Base Stations
Software Defined Radios
Portable Medical Imaging
Multi-Channel Data Acquisition
Nondestructive Testing
S/H
S/H
GND
CONTROL
CLOCK
ADC CORE
ADC CORE
16-BIT
16-BIT
P-P
1.8V
V
DD
to 2V
P-P
DRIVERS
OUTPUT
1.8V
OV
OGND
DD
218210 TA01a
D1_15
D1_0
D2_15
D2_0
40Msps/25Msps Low Power
DESCRIPTION
The LTC
multaneous sampling 16-bit A/D converters designed for
digitizing high frequency, wide dynamic range signals. They
are perfect for demanding communications applications
with AC performance that includes 77dB SNR and 90dB
spurious free dynamic range (SFDR). Ultralow jitter of
0.07ps
excellent noise performance.
DC specs include ±2LSB INL (typ), ±0.5LSB DNL (typ)
and no missing codes over temperature. The transition
noise is 3.3LSB
The digital outputs can be either full rate CMOS, Double
Data Rate CMOS, or Double Data Rate LVDS. A separate
output power supply allows the CMOS output swing to
range from 1.2V to 1.8V.
The ENC
or single-ended with a sine wave, PECL, LVDS, TTL, or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
LTC2182/LTC2181/LTC2180
CMOS,
DDR CMOS
OR DDR LVDS
OUTPUTS
RMS
®
+
2182/LTC2181/LTC2180 are two-channel si-
and ENC
allows undersampling of IF frequencies with
RMS
.
–100
–110
–120
–10
–20
–30
–40
–50
–60
–70
–80
–90
inputs may be driven differentially
0
2-Tone FFT, f
0
16-Bit, 65Msps/
10
FREQUENCY (MHz)
Dual ADCs
IN
= 70MHz and 69MHz
20
218210 TA01b
30
218210f
1

Related parts for ltc2182

ltc2182 Summary of contents

Page 1

... ANALOG S/H ADC CORE INPUT 65MHz CLOCK CLOCK CONTROL GND LTC2182/LTC2181/LTC2180 40Msps/25Msps Low Power DESCRIPTION The LTC ® 2182/LTC2181/LTC2180 are two-channel si- multaneous sampling 16-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. They are perfect for demanding communications applications with AC performance that includes 77dB SNR and 90dB spurious free dynamic range (SFDR) ...

Page 2

... EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB 2 (Notes 1, 2) Digital Output Voltage ................ –0.3V to (OV Operating Temperature Range + 0.2V) LTC2182C, LTC2181C, LTC2180C ............. 0°C to 70°C DD LTC2182I, LTC2181I, LTC2180I ............–40°C to 85°C Storage Temperature Range .................. –65°C to 150°C DOUBLE DATA RATE CMOS OUTPUT MODE 48 D1_5 ...

Page 3

... T = 28°C/W JMAX JA EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB PART MARKING* PACKAGE DESCRIPTION LTC2182UP 64-Lead (9mm × 9mm) Plastic QFN LTC2182UP 64-Lead (9mm × 9mm) Plastic QFN LTC2181UP 64-Lead (9mm × 9mm) Plastic QFN LTC2181UP 64-Lead (9mm × 9mm) Plastic QFN LTC2180UP 64-Lead (9mm × ...

Page 4

... Sample-and-Hold Acquisition Delay Time AP t Sample-and-Hold Acquisition Delay Jitter JITTER CMRR Analog Input Common Mode Rejection Ratio BW-3B Full-Power Bandwidth 4 The denotes the specifications which apply over the full operating l = 25°C. (Note 5) A LTC2182 MIN TYP MAX 16 l –6 ± –0.9 ±0.5 0.9 l –7 ± ...

Page 5

... REF OUT V Output Temperature Drift REF V Output Resistance –400µA < I REF V Line Regulation 1.7V < V REF LTC2182/LTC2181/LTC2180 The denotes the specifications which apply over the full operating temperature range –1dBFS. (Note 5) IN LTC2182 MIN TYP MAX 77 75.6 76.9 l 76.8 76 ...

Page 6

... LTC2182/LTC2181/LTC2180 DIGITAL INPUTS AND OUTPUTS temperature range, otherwise specifications are at T SYMBOL PARAMETER + – ENCODE INPUTS (ENC , ENC ) – Differential Encode Mode (ENC Not Tied to GND) V Differential Input Voltage ID V Common Mode Input Voltage ICM V Input Voltage Range IN R Input Resistance ...

Page 7

... DD 1.7 1.8 1.9 l 1.7 1.8 1 106 237 304 341 The denotes the specifications which apply over the full operating temperature l = 25°C. (Note 5) LTC2182 MIN TYP MAX 7.3 7.69 500 l 2 7.69 500 l 7.3 7.69 500 l 2 7.69 500 l 0 CONDITIONS C = 5pF (Note ...

Page 8

... IC, not per channel. Note 10: Recommended operating conditions. + – /ENC = MIN TYP MAX 1.1 1.8 3 1.5 2 0.3 0 250 125 l = 65MHz (LTC2182), 40MHz (LTC2181), or SAMPLE + = single-ended 1.8V square with differential drive, 5pF load on P-P UNITS Cycles 218210f ...

Page 9

... INPUT – ENC + ENC D1_0_1 • • • D1_14_15 D2_0_1 • • • D2_14_15 OF2_1 + CLKOUT – CLKOUT LTC2182/LTC2181/LTC2180 Full-Rate CMOS Output Mode Timing All Outputs Are Single-Ended and Have CMOS Levels – ...

Page 10

... LTC2182/LTC2181/LTC2180 TIMING DIAGRAMS CH 1 ANALOG INPUT CH 2 ANALOG INPUT – ENC + ENC + D1_0_1 – D1_0_1 • • • + D1_14_15 – D1_14_15 + D2_0_1 – D2_0_1 • • • + D2_14_15 – D2_14_15 + OF2_1 – OF2_1 + CLKOUT – CLKOUT SCK SDI R/W SDO ...

Page 11

... LTC2182: Shorted Input Histogram 10000 9000 8000 7000 6000 5000 4000 3000 2000 1000 0 32831 32837 32843 32849 32855 OUTPUT CODE 218210 G08 LTC2182: 64k Point FFT 5MHz IN –1dBFS, 65Msps 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 10 ...

Page 12

... LTC2181: Differential Non-Linearity (DNL) 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 16384 32768 49152 65536 OUTPUT CODE 218210 G17 LTC2182: SFDR vs Input Level 70MHz, 65Msps, 2V Range IN 130 120 dBFS 110 100 90 dBc –80 –70 –60 –50 –40 –30 –20 –10 ...

Page 13

... Input Frequency, –1dBFS, 40Msps, 2V Range 100 95 90 3RD 85 80 2ND 100 150 200 250 300 INPUT FREQUENCY (MHz) 218210 G25 LTC2182/LTC2181/LTC2180 LTC2181: 64k Point FFT 70MHz, –1dBFS, 40Msps IN 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 ...

Page 14

... LTC2182/LTC2181/LTC2180 TYPICAL PERFORMANCE CHARACTERISTICS LTC2181 Sample Rate, VDD 5MHz, –1dBFS, Sine Wave Input on Each Channel 80 70 3.5mA LVDS OUTPUTS 60 CMOS OUTPUTS SAMPLE RATE (Msps) 218210 G28 LTC2180: Integral Non-Linearity (INL) 4.0 3.0 2.0 1.0 0 –1.0 –2.0 –3.0 –4.0 0 32768 49152 65536 ...

Page 15

... Sine Wave Input on Each Channel 50 3.5mA LVDS OUTPUTS 45 40 CMOS OUTPUTS SAMPLE RATE (Msps) 218210 G43 LTC2182/LTC2181/LTC2180 LTC2180: Shorted Input Histogram 10000 9000 8000 7000 6000 5000 4000 3000 2000 1000 0 32836 32848 32854 32860 ...

Page 16

... LTC2182/LTC2181/LTC2180 PIN FUNCTIONS PINS THAT ARE THE SAME FOR ALL DIGITAL OUTPUT MODES V (Pins 1, 16, 17, 64): Analog Power Supply, 1. 1.9V. Bypass to ground with 0.1µF ceramic capacitors. Adjacent pins can share a bypass capacitor. V (Pin 2): Common Mode Bias Output, nominally equal CM1 to V /2. V ...

Page 17

... D2_0_1 to D2_14_15 (Pins 24, 26, 28, 30, 32, 34, 36, 38): Channel 2 Double Data Rate Digital Outputs. Two data bits are multiplexed onto each output pin. The even data bits (D0, D2, D4, D6, D8, D10, D12, D14) appear when LTC2182/LTC2181/LTC2180 + CLKOUT D11, D13, D15) appear when CLKOUT DNC (Pins 23, 25, 27, 29, 31, 33, 35, 37, 43, 45, 47, 49, 51, 53, 55, 57, 59): Do not connect these pins ...

Page 18

... LTC2182/LTC2181/LTC2180 PIN FUNCTIONS – + – D1_0_1 /D1_0_1 to D1_14_15 /D1_14_15 45/46, 47/48, 49/50, 51/52, 53/54, 55/56, 57/58): Chan- nel 2 Double Data Rate Digital Outputs. Two data bits are multiplexed onto each differential output pair. The even data bits (D0, D2, D4, D6, D8, D10, D12, D14) appear when + CLKOUT is low. The odd data bits (D1, D3, D5, D7, D9, ...

Page 19

... APPLICATIONS INFORMATION CONVERTER OPERATION The LTC2182/LTC2181/LTC2180 are low power, two- channel, 16-bit, 65Msps/40Msps/25Msps A/D convert- ers that are powered by a single 1.8V supply. The analog inputs should be driven differentially. The encode input can be driven differentially, or single ended for lower power consumption. The digital outputs can be CMOS, ...

Page 20

... Figure 5. Recommended Front-End Circuit for Input Frequencies from 150MHz to 250MHz 20 Reference The LTC2182/LTC2181/LTC2180 has an internal 1.25V voltage reference. For a 2V input range using the internal reference, connect SENSE to V using the internal reference, connect SENSE to ground. For a 2V input range with an external reference, apply a 1 ...

Page 21

... Figure 13). The encode inputs are internally biased to 1.2V 218210 F08b through 10kΩ equivalent resistance. The encode inputs can be taken above V mode range is from 1.1V to 1.6V. In the differential encode V REF 2.2µF LTC2182 1.25V SENSE EXTERNAL REFERENCE 1µF 218210 F09 (up to 3.6V), and the common ...

Page 22

... F12 DIGITAL OUTPUTS Digital Output Modes The LTC2182/LTC2181/LTC2180 can operate in three digital output modes: full rate CMOS, double data rate CMOS (to halve the number of output lines), or double data rate LVDS (to reduce digital noise in the system.) The output mode is set by mode control register A3 (serial programming mode SCK (parallel programming mode) ...

Page 23

... D2_0_1 through D2_14_15 /D2_14_15 + output data. Overflow (OF2_1 /OF2_1 LTC2182/LTC2181/LTC2180 output clock (CLKOUT output pair. Note that the overflow for both ADC channels is multiplexed onto the OF2_1 ) have CMOS output By default the outputs are standard LVDS levels: 3.5mA and OGND which output current and a 1 ...

Page 24

... CLKOUT signal may need to be phase shifted relative to the data output bits. Most FPGAs have this feature; this is generally the best place to adjust the timing. The LTC2182/LTC2181/LTC2180 can also phase shift the + – CLKOUT ...

Page 25

... A4. LTC2182/LTC2181/LTC2180 CLKOUT OF D15 D14 • • • D2 RANDOMIZER Figure 15. Functional Equivalent of Digital Output Randomizer PC BOARD FPGA CLKOUT OF D15/D0 D14/D0 LTC2182 D2/D0 D1/D0 D0 Figure 16. Unrandomizing a Randomized Digital Output Signal CLKOUT OF D15/D0 D14/D0 D2/D0 D1/D0 D0 218210 F15 D15 D14 • • • D2 ...

Page 26

... A1 (serial programming mode SDI and SDO (parallel programming mode). DEVICE PROGRAMMING MODES The operating modes of the LTC2182/LTC2181/LTC2180 can be programmed by either a parallel interface or a simple serial interface. The serial interface has more flex- ibility and can program all available modes. The parallel interface is more limited and can only program some of the more commonly used modes ...

Page 27

... HEAT TRANSFER Most of the heat generated by the LTC2182/LTC2181/ LTC2180 is transferred from the die through the bottom- side exposed pad and package leads onto the printed circuit board. For good electrical and thermal performance, the exposed pad must be soldered to a large grounded pad on the PC board ...

Page 28

... LTC2182/LTC2181/LTC2180 APPLICATIONS INFORMATION Table 3. Serial Programming Mode Register Map (PAR/SER = GND) REGISTER A0: RESET REGISTER (ADDRESS 00h RESET X Bit 7 RESET Software Reset Bit 0 = Not Used 1 = Software Reset. All Mode Control Registers Are Reset to 00h. The ADC Is Momentarily Placed in SLEEP Mode. This Bit Is Automatically Set Back to Zero at the End of the SPI Write Command ...

Page 29

... Data Output Randomizer Mode Control Bit 0 = Data Output Randomizer Mode Off 1 = Data Output Randomizer Mode On Bit 0 TWOSCOMP Two’s Complement Mode Control Bit 0 = Offset Binary Data Format 1 = Two’s Complement Data Format LTC2182/LTC2181/LTC2180 ILVDS0 TERMON Digital Output Mode Control Bits D5 ...

Page 30

... LTC2182/LTC2181/LTC2180 TYPICAL APPLICATIONS 30 Silkscreen Top Top Side 218210f ...

Page 31

... TYPICAL APPLICATIONS LTC2182/LTC2181/LTC2180 Inner Layer 2 GND Inner Layer 3 218210f 31 ...

Page 32

... LTC2182/LTC2181/LTC2180 TYPICAL APPLICATIONS 32 Inner Layer 4 Inner Layer 5 Power 218210f ...

Page 33

... TYPICAL APPLICATIONS LTC2182/LTC2181/LTC2180 Bottom Side 218210f 33 ...

Page 34

... LTC2182 9 REFH 10 REFL 11 PAR/SER IN2 13 – A IN2 14 GND 15 V CM2 C18 0.1µF C78 0.1µF C79 0.1µF R51 100 ENCODE CLOCK LTC2182 Schematic DIGITAL OUTPUTS 48 + D1_4_5 47 – D1_4_5 46 + D1_2_3 45 – D1_2_3 44 + D1_0_1 43 – D1_0_1 C37 41 OGND 0.1µ CLKOUT 39 – ...

Page 35

... Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. LTC2182/LTC2181/LTC2180 UP Package 64-Lead Plastic QFN (9mm × 9mm) (Reference LTC DWG # 05-08-1705 Rev C) 0.70 ± ...

Page 36

... LTC2182/LTC2181/LTC2180 TYPICAL APPLICATION RELATED PARTS PART NUMBER DESCRIPTION ADCs LTC2259-14/LTC2260-14/ 14-Bit, 80Msps/105Msps/125Msps LTC2261-14 1.8V ADCs, Ultralow Power LTC2262-14 14-Bit, 150Msps 1.8V ADC, Ultralow Power LTC2266-14/LTC2267-14/ 14-Bit, 80Msps/105Msps/125Msps LTC2268-14 1.8V Dual ADCs, Ultralow Power LTC2266-12/LTC2267-12/ 12-Bit, 80Msps/105Msps/125Msps LTC2268-12 1.8V Dual ADCs, Ultralow Power LTC2208 16-Bit, 130Msps 3 ...

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