mcf52258 Freescale Semiconductor, Inc, mcf52258 Datasheet - Page 13

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mcf52258

Manufacturer Part Number
mcf52258
Description
Mcf52259 Coldfire Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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higher period and duty cycle resolution, each pair of adjacent channels ([7:6], [5:4], [3:2], and [1:0]) can be concatenated to
form a single 16-bit channel. The module can, therefore, be configured to support 8/0, 6/1, 4/2, 2/3, or 0/4 8-/16-bit channels.
1.2.21
The watchdog timer is a 32-bit timer that facilitates recovery from runaway code. The watchdog counter is a free-running
down-counter that generates a reset on underflow. To prevent a reset, software must periodically restart the countdown.
1.2.22
The backup watchdog timer is an independent 16-bit timer that, like the software watchdog timer, facilitates recovery from
runaway code. This timer is a free-running down-counter that generates a reset on underflow. To prevent a reset, software must
periodically restart the countdown. The backup watchdog timer can be clocked by either the relaxation oscillator or the system
clock.
1.2.23
The clock module contains a crystal oscillator, 8 MHz on-chip relaxation oscillator (OCO), phase-locked loop (PLL), reduced
frequency divider (RFD), low-power divider status/control registers, and control logic. To improve noise immunity, the PLL,
crystal oscillator, and relaxation oscillator have their own power supply inputs: VDDPLL and VSSPLL. All other circuits are
powered by the normal supply pins, VDD and VSS.
1.2.24
The device has two interrupt controllers that supports up to 128 interrupt sources. There are 56 programmable sources, 49 of
which are assigned to unique peripheral interrupt requests. The remaining seven sources are unassigned and may be used for
software interrupt requests.
1.2.25
The direct memory access (DMA) controller provides an efficient way to move blocks of data with minimal processor
intervention. It has four channels that allow byte, word, longword, or 16-byte burst line transfers. These transfers are triggered
by software explicitly setting a DCRn[START] bit or by the occurrence of certain UART or DMA timer events.
1.2.26
The reset controller determines the source of reset, asserts the appropriate reset signals to the system, and keeps track of what
caused the last reset. There are seven sources of reset:
Control of the LVD and its associated reset and interrupt are managed by the reset controller. Other registers provide status flags
indicating the last source of reset and a control bit for software assertion of the RSTO pin.
Freescale Semiconductor
External reset input
Power-on reset (POR)
Watchdog timer
Phase locked-loop (PLL) loss of lock / loss of clock
Software
Low-voltage detector (LVD)
JTAG
Software Watchdog Timer
Backup Watchdog Timer
Phase-Locked Loop (PLL)
Interrupt Controllers (INTCn)
DMA Controller
Reset
MCF52259 ColdFire Microcontroller, Rev. 1
Family Configurations
13

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