st5092 STMicroelectronics, st5092 Datasheet - Page 3

• Manufacturer Part Number: st5092
• Description: 2.7v Supply 14-bit Linear Codec With High-performance Audio Front-end
• Manufacturer: STMicroelectronics

PIN FUNCTIONS (SO28)
Pin
5,6
7,8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1
2
3
4
9
V
V
MIC2+
Name
GNDP
MIC1+
GNDA
MIC3+
MCLK
MIC2-
MIC1-
MIC3-
Fr+
Lr+
CCLK
GND
V
V
N.C.
N.C.
CS-
V
CO
LO
D
BZ
D
FS
CI
CCA
CCP
, V
, V
CC
R
X
Fr–
Lr–
Not Connected.
Positive power supply input for the analog section.
V
Positive power supply input for the power section. V
Not Connected.
Receive analog earpiece amplifier complementary outputs. These outputs can drive directly earpiece
transductor. The signal at this output can be the sum of:
- Receive Speech signal from D
- Internal Tone Generator,
- Sidetone signal.
Receive analog extra amplifier complementary outputs. The signal at these outputs can be the
sum of:
- Receive Speech signal from DR,
- Internal Tone generator,
- Sidetone signal.
Power ground. V
together close to the device.
Receive data input: Data is shifted in during the assigned Received time slots In delayed and non-
delayed normal frame synchr. modes voice data byte is shifted in at the MCLK frequency on the
falling edges of MCLK, while in non-delayed reverse frame synchr. mode voice data byte is shifted in
at the MCLK frequency on the rising edges of MCLK.
Control Clock input: This clock shifts serial control information into CI and out from CO when the
CS- input is low, depending on the current instruction. CCLK may be asynchronous with the other
system clocks.
Chip Select input: When this pin is low, control information is written into and out from the ST5092
via CI and CO pins.
Control data Input: Serial Control information is shifted into the ST5092 on this pin when CS- is low
on the rising edges of CCLK.
Pulse width modulated buzzer driver output.
Positive power supply input for the digital section.
Control data Output: Serial control/status information is shifted out from the ST5092 on this pin
when CS- is low on the falling edges of CCLK.
Transmit Data ouput: Data is shifted out on this pin during the assigned transmit time slots.
Elsewhere D
synchr. modes, voice data byte is shifted out from TRISTATE output D
edge of MCLK, while in non-delayed reverse frame synchr mode voice data byte is shifted out on
the falling edge of MCLK.
Ground: All digital signals are referenced to this pin.
Frame Sync input: This signal is a 8kHz clock which defines the start of the transmit and receive
frames. Any of three formats may be used for this signal: non delayed normal mode, delayed
mode, and non delayed reverse mode.
Master Clock Input: This signal is used by the switched capacitor filters and the encoder/decoder
sequencing logic. Values must be 512 kHz, 1.536 MHz, 2.048 MHz or 2.56 MHz selected by means of
Control Register CRO. MCLK is used also to shift-in and out data.
A logic 1 written into DO (CR1) appears at LO pin as a logic 0
A logic 0 written into DO (CR1) appears at LO pin as a logic 1.
Second negative high impedance input to transmit pre-amplifier for microphone connection.
Second Positive high impedance input to transmit pre-amplifier for microphone connection.
Negative high impedance input to transmit pre-amplifier for microphone connection.
Positive high impedance input to transmit pre-amplifier for microphone connection.
Analog Ground: All analog signals are referenced to this pin. GND and GNDA must be connected
together close to the device.
Third negative high impedance output to transmit preamplifier for microphone connection.
Third positive high impedance output to transmit preamplifier for microphone connection.
CC
and V
CCA
X
output is in the high impedance state. In delayed and non-delayed normal frame
must be directly connected together.
Fr
and V
Lr
driver are referenced to this pin. GNDP and GND must be connected
R
,
Description
CCP
and V
CC
must be connected together.
X
at the MCLK on the rising
ST5092
3/29