ltc2978 Linear Technology Corporation, ltc2978 Datasheet - Page 7

• Manufacturer Part Number: ltc2978
• Description: Octal Pmbus Power Supply Monitor And Controller With Eeprom
• Manufacturer: Linear Technology Corporation

elecTrical characTerisTics
temperature range, otherwise specifications are at T
otherwise indicated. C
SYMBOL
Digital Outputs SDA, ALERTB, PWRGD, SHARE_CLK, FAULTB00, FAULTB01, FAULTB10, FAULTB11
V
f
Digital Inputs ASEL0,ASEL1
V
V
I
I
C
Serial Bus Timing Characteristics
f
t
t
t
t
t
t
t
t
t
t
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating for extended periods may affect device reliability and
lifetime.
Note 2: All currents into device pins are positive. All currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified. If power is supplied to the chip via the V
V
Note 3: Hysteresis in the output voltage is created by package stress that
differs depending on whether the IC was previously at a higher or lower
temperature. Output voltage is always measured at 25°C, but the IC is
cycled to 85°C or –40°C before successive measurements. Hysteresis is
roughly proportional to the square of the temperature change.
Note 4: TUE(%) is defined as:
Note 5: Integral nonlinearity (INL) is defined as the deviation of a code
from a straight line passing through the actual endpoints of the transfer
curve (0V and 6V). The deviation is measured from the center of the
quantization band.
SHARE_CLK_OUT
IH,IL
IH, Z
SCL
LOW
HIGH
BUF
HD,STA
SU,STA
SU,STO
HD,DAT
SU,DAT
SP
TIMEOUT_BUS
OL
IH
IL
IN
PWR
Gain Error (%) + 100 • (INL + V
and V
DD33
PARAMETER
Digital Output Low Voltage
Output Frequency Operating Range
Input High Threshold Voltage
Input Low Threshold Voltage
High, Low Input Current
Hi-Z Input Current
Input Capacitance
Serial Clock Frequency (Note 10)
Serial Clock Low Period (Note 10)
Serial Clock High Period (Note 10)
Bus Free Time Between Stop and Start
(Note 10)
Start Condition Hold Time (Note 10)
Start Condition Setup Time (Note 10)
Stop Condition Setup Time (Note 10)
Data Hold Time (LTC2978 Receiving
Data) (Note 10)
Data Hold Time (LTC2978 Transmitting
Data) (Note 10)
Data Setup Time (Note 10)
Pulse Width of Spike Suppressed
(Note 10)
Time Allowed to Complete any PMBus
Command After Which Time SDA Will
Be Released and Command Terminated
pins together.
VDD33
= 100nF , C
OS
)/V
IN
.
VDD25
DD33
= 100nF and C
pin only, connect
CONDITIONS
I
5.49kΩ Pull-Up to V
ASEL[1:0] = 0, V
Longer Timeout = 0
Longer Timeout = 1
SINK
A
= 3mA
= 25°C. V
The
REF
= 100nF .
l
PWR
DD33
denotes the specifications which apply over the full operating
DD33
= V
Note 6: The time between successive ADC conversions (latency of the
ADC) for any given channel is given as: 36.9ms + (6.15ms • number of
ADC channels configured in Low Resolution mode) + (24.6ms • number of
ADC channels configured in High Resolution mode).
Note 7: Nonlinearity is defined from the first code that is greater than or
equal to the maximum offset specification to full-scale code, 1023.
Note 8: EEPROM endurance and retention are guaranteed by design,
characterization and correlation with statistical process controls. The
minimum retention specification applies for devices whose EEPROM has
been cycled less than the minimum endurance specification.
Note 9: The LTC2978 will not acknowledge any PMBus write commands
when a STORE_USER_ALL command is being executed.
Note 10: Maximum capacitive load, C
and clock rise time (t
300ns and (20 + 0.1 • C
line in pF . SCL and SDA external pull-up voltage, V
IN_SNS
= 12V; V
DD33
r
) and fall time (t
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
B
, V
) (ns) < t
V
DD25
DD33
MIN
600
600
600
300
100
1.3
0.6
1.3
90
10
0
and REF pins floating, unless
– 0.5
f
< 300ns. C
B
f
) are: (20 + 0.1• C
, for SCL and SDA is 400pF . Data
TYP
100
200
10
98
25
B
= capacitance of one bus
IO
, is 3.13V < V
LTC2978
MAX
B
110
±95
±24
400
900
280
0.4
0.5
) (ns) < t
35
IO
r
<
< 5.5V.
UNITS
2978fa

kHz
kHz
ms
ms
µA
µA
pF
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
V
V
V