irs2548d International Rectifier Corp., irs2548d Datasheet - Page 17

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irs2548d

Manufacturer Part Number
irs2548d
Description
Smps/led Driver Pfc + Half-bridge Control Ic
Manufacturer
International Rectifier Corp.
Datasheet

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DC Bus Over-voltage Protection
Should over-voltage occur on the DC bus and the
VBUS pin exceeds the internal 4.3V threshold
(VBUSOV+), the PFC output is disabled (set to a
logic ‘low’). When the DC bus decreases again
and the VBUS pin decreases below the internal
4.15V threshold (VBUSOV-), a watch-dog pulse is
forced on the PFC pin and normal PFC operation
is resumed.
Figure 13: On-time modulation circuit timing diagram
I
PFC
LPFC
pin
0
0
near peak region of
rectified AC line
near zero-crossing region
of rectified AC line
17
III. Design Equations (Half-Bridge)
Note: The results from the following design equations
can differ slightly from actual measurements due to IC
tolerances, component tolerances, and oscillator over-
and under-shoot due to internal comparator response
time.
Step 1: Program Run Frequency
The run frequency is programmed with the timing
resistor RFMIN at the FMIN pin.
The graph in Figure 14 (RFMIN vs. Frequency) can be
used to select RFMIN value for desired run frequency.
Step 2: Program Maximum Current
The maximum current is programmed with the external
resistor RCS and an internal threshold of 1.25V
(VCSTH+). This threshold determines the over-current
limit of the system:
or
180
160
140
120
100
I
R
80
60
40
20
MAX
CS
Figure 13: Graph of frequency against RFMIN
10
=
=
I
. 1
. 1
R
MAX
25
15
25
CS
20
Equivalent RFMIN (Kohms)
25
30
© 2011 International Rectifier
[Ohms]
[Amps Peak]
35
IRS2548D
40
45
50

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