ir3500a International Rectifier Corp., ir3500a Datasheet - Page 9

• Manufacturer Part Number: ir3500a
• Description: Xphase3 Vr11.0 & Amd Pvid Control Ic
• Manufacturer: International Rectifier Corp.

SYSTEM THEORY OF OPERATION
PWM Control Method
The PWM block diagram of the XPhase3
with trailing edge modulation is used. A high-gain wide-bandwidth voltage type error amplifier in the Control IC is
used for the voltage control loop. Input voltage is sensed in phase ICs and feed-forward control is realized. The
PWM ramp slope will change with the input voltage and automatically compensate for changes in the input voltage.
The input voltage can change due to variations in the silver box output voltage or due to the wire and PCB-trace
voltage drop related to changes in load current.
Frequency and Phase Timing Control
The oscillator and system clock frequency is programmable from 250kHz to 9MHZ by an external resistor (ROSC).
The control IC system clock signal (CLKOUT) is connected to CLKIN of all the phase ICs. The phase timing of the
phase ICs is controlled by the daisy chain loop, where control IC phase clock output (PHSOUT) is connected to the
phase clock input (PHSIN) of the first phase IC, and PHSOUT of the first phase IC is connected to PHSIN of the
LDO AMPLIFIER
ERROR
AMPLIFIER
IVSETPT
CONTROL IC
CLOCK GENERATOR
Page 9 of 47
REMOTE SENSE
AMPLIFIER
+
-
IROSC
VDAC
+
-
+
-
VDRP
AMP
VSETPT
VDRP
IIN
PHSOUT
PHSIN
VO
VDAC
LGND
EAOUT
FB
CLKOUT
RVSETPT
RCOMP
CCOMP
CCOMP1
RFB1
CFB
RDRP1
CDRP
GATE DRIVE
VOLTAGE
RFB
RDRP
TM
Figure 4 - PWM Block Diagram
architecture is shown in Figure 4. Feed-forward voltage mode control
PHSOUT
PHSOUT
PHSIN
CLKIN
ISHARE
DACIN
EAIN
ISHARE
DACIN
CLKIN
PHSIN
EAIN
3K
3K
CLK
D
SHARE ADJUST
ERROR AMPLIFIER
CLK
D
SHARE ADJUST
ERROR AMPLIFIER
Q
PWM
COMPARATOR
Q
PWM
COMPARATOR
+
-
+
-
RAMP
DISCHARGE
CLAMP
RAMP
DISCHARGE
CLAMP
ENABLE
ENABLE
1
-
1
VID6
-
VID6
+
VID6
VID6
+
VID6
VID6
-
+
-
+
+
-
+
-
PHASE IC
PHASE IC
2
2
PWM LATCH
1
2
PWM LATCH
BODY
BRAKING
COMPARATOR
1
2
BODY
BRAKING
COMPARATOR
DOMINANT
D
CLK
DOMINANT
RESET
D
CLK
RESET
VID6
VID6
VID6
VID6
Q
Q
Q
Q
+
4
5
+
4
5
+
+
CURRENT
SENSE
AMPLIFIER
CURRENT
SENSE
AMPLIFIER
+
-
+
-
CSIN-
CSIN-
VCC
VCCH
GATEH
SW
VCCL
GATEL
PGND
CSIN+
VCC
VCCH
GATEH
SW
VCCL
GATEL
PGND
CSIN+
CCS
CCS
RCS
RCS
July 3, 2008
CBST
CBST
IR3500A
COUT
VIN
VOSNS+
VOUT
GND
VOSNS-