ir3500a International Rectifier Corp., ir3500a Datasheet - Page 31

• Manufacturer Part Number: ir3500a
• Description: Xphase3 Vr11.0 & Amd Pvid Control Ic
• Manufacturer: International Rectifier Corp.

The soft start delay time (TD1) and VR ready delay time (TD3) are determined by (8) to (9) respectively.
Once C
VDAC Slew Rate Programming Capacitor C
The slew rate of VDAC down-slope SR
(11), where I
slope. The resistor R
Over Current Setting Resistor R
The inductor DC resistance is utilized to sense the inductor current. The copper wire of inductor has a constant
temperature coefficient of 3850 ppm/° C, and therefore the maximum inductor DCR can be calculated from (13),
where R
T_
The total input offset voltage (V
(V
sense resistor R
The over-current limit is set by the external resistor R
peak to peak ripple of the net inductor current is much smaller than the stand alone phase due to interleaving.
The ratio of the peak to average current in this case can be approximated using (16).
Where; I
CS_OFST)
ROOM
SS/DEL
G
D=Vo/V
Page 31 of 47
LIMIT
L_MAX
respectively.
CS
=Over current limit, n=Number of phases, K
=Gain of the current sense amplifier, I
of the amplifier itself and that created by the amplifier input bias current flowing through the current
SINK
is chosen, the minimum over-current fault latch delay time
and R
I
CS
, m=Maximum integer that doesn’t exceed (n*D)
is the sink current of VDAC pin. The slew rate of VDAC up-slope is the same as that of down-
.
VDAC
L_ROOM
TD
TD
V
t
C
K
R
R
R
OCDEL
CS
VDAC
OCSET
VDAC
L
P
is used to compensate VDAC circuit and can be calculated as follows
1
3
_
=
_
MAX
=
=
TOFST



V
C
C
=
are the inductor DCR at maximum temperature T
=
I
=
=
SS
SS
0
⋅
=
SR
CS_TOFST
[
D
5 .
(
OCSET
C
/
I
I
I
/
I
R
=
DEL
CHG
DEL
LIMIT
LIMIT
⋅
SINK
DOWN
+
SS
L
1 (
V
n
_
I
I
3
CS
/
−
1 *
ROOM
CHG
DEL
*
2 .
DISCHG
C
/
DOWN
D
_
n
4 (
∗
4 .
VDAC
∗
OFST
)
)
=
R
⋅
0 .
10
⋅
*
) of current sense amplifier in phase ICs is the sum of input offset
L
=
L
n
44
SR
∗
−
. 0
_
⋅
⋅
−
2
C
1 [
(
15
MAX
V
f
+
VDAC
can be programmed by the external capacitor C
D
52
12
*
sw
DOWN
SS
O
10
+
I
−
⋅
5 .
CSIN
/
)
3850
2
DEL
∗
OCSET
−
=
m
n
=
*
⋅
6
1 (
D
10
)
and Resistor R
C
+
C
⋅
1 *
+
⋅
(
OCSET
∗
−
SS
*
1 (
SS
m
K
= Determined by the ROSC and given by Figure 24,
6
55
P
4 .
10
R
/
n
−
=Ratio of the peak to average current for the inductor,
/
P
+
52
DEL
CS
DEL
)
D
−
1
*
6
+
5 .
)
−
10
∗
V
*
*
and is given by (15). In a multiphase architecture the
*
D
CS
4 (
(
10
T
−
)
. 0



0 .
6
L
_
−
12
TOFST
_
6
−
MAX
V
VDAC
O
]
)
−
∗
T
G
t
ROOM
CS
OCDEL
/
I
OCSET
)]
is fixed and can be quantified as
L_MAX
(16)
(8)
(9)
(11)
(12)
(13)
(14)
(15)
and room temperature
July 3, 2008
VDAC
IR3500A
(10)
as defined in