asm2i99456 PulseCore Semiconductor, asm2i99456 Datasheet - Page 6

• Manufacturer Part Number: asm2i99456
• Description: 3.3v/2.5v Lvcmos Clock Fanout Buffer
• Manufacturer: PulseCore Semiconductor

November 2006
rev 0.3
Table 9. AC Characteristics
Note: 1 AC characteristics apply for parallel output termination of 50Ω  t o V
Table 10. AC Characteristics
Note: 1 AC characteristics apply for parallel output termination of 50Ω  t o V
Symbol
Symbol
t
t
t
V
t
t
PLZ
PLH,HL
t
PZL
t
t
DC
P
t
DC
sk(PP)
t
SK(P)
f
sk(PP)
sk(O)
V
t
t
t
SK(P)
t
sk(O)
MAX
CMR
,
f
r
PLH
PHL
r
4 Violation of the 1.0nS maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width,
2 The ASM2I99456 is functional up to an input and output clock frequency of 350MHz and is characterized up to 250 MHz.
3 V
5 Output pulse skew is the absolute difference of the propagation delay times: | t
2 For all other AC specifications, refer to 2.5V or 3.3V tables according to the supply voltage of the output bank.
3 Output pulse skew is the absolute difference of the propagation delay times: | t
ref
, t
, t
PP
REF
,
,
Q
Q
swing lies within the V
f
HZ
f
output duty cycle and maximum frequency specifications.
LZ
CMR
3
(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V
Device-to-device Skew
Propagation delay
Output pulse skew
Output Duty Cycle
Input Frequency
Maximum Output Frequency
Peak-to-peak input voltage
Common Mode Range
Reference Input Pulse Width
PCLK Input Rise/Fall Time
Propagation delay
Output Disable Time
Output Enable Time
Device-to-device Skew
Output pulse skew
Output Duty Cycle
Output Rise/Fall Time
Output-to-output
Output-to-output
Skew
Skew
PP
(AC) specification.
3
Characteristics
5
Characteristics
(VCC = VCCA = VCCB = VCCC = 2.5V ± 5%, T
Notice: The information in this document is subject to change without notice.
(VCC = 3.3V ± 5%, VCCA = VCCB = VCCC = 2.5V ± 5% or 3.3V ± 5%,T
3.3V/2.5V LVCMOS Clock Fanout Buffer
Any output, Any output divider
Any output bank, same output
Any output, Any output divider
Any output bank, same output
Within one bank
÷1 or ÷2 output
PCLK to any Q
PCLK to any Q
Within one bank
÷1 or ÷2 output
PCLK to any Q
÷1 output
÷2 output
TT
TT
divider
.
.
PCLK
PCLK
divider
PLH
PLH
Min
500
1.1
1.4
2.6
2.6
0.1
- t
- t
A
45
0
0
0
PHL
PHL
= -40 to +85°C)
Min
45
|.
|.
Typ
50
See 3.3V table
Typ
50
1
VCC-0.7
1000
250
250
Max
A
1.0
125
150
200
350
200
Max
5.6
5.5
3.0
1.0
150
250
350
250
10
10
55
2.5
= -40 to +85°C)
55
4
2
2
ASM2I99456
Unit
MHz
MHz
MHz
pS
Unit
mV
pS
pS
pS
nS
pS
nS
nS
nS
nS
nS
nS
pS
pS
nS
pS
nS
%
%
V
CMR
,1,2
range and the input
DC
DC
0.7 to 1.7V
0.6 to 1.8V
Condition
Condition
FSELx=1
FSELx=0
LVPECL
LVPECL
6 of 14
REF
REF
= 50%
= 50%