cs844256bgit Integrated Device Technology, cs844256bgit Datasheet - Page 10

• Manufacturer Part Number: cs844256bgit
• Description: Femtoclocks? Crystal-to-lvds Frequency Synthesizer W/integrated Fanout Buffer
• Manufacturer: Integrated Device Technology

LVCMOS
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC couple capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it
is recommended that the amplitude be reduced from full swing
to half swing in order to prevent signal interference with the
power rail and to reduce noise. This configuration requires that
the output impedance of the driver (Ro) plus the series
3.3V, 2.5V LVDS D
A general LVDS interface is shown in Figure 4. In a 100
differential transmission line environment, LVDS drivers
IDT
ICS844256I
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
™
/ ICS
™
LVDS FREQUENCY SYNTHESIZER W/FANOUT BUFFER
TO
XTAL I
RIVER
NTERFACE
F
IGURE
T
ERMINATION
3. G
VDD
VCC
V
DD
Ro
LVDS_Driv er
ENERAL
100 Ohm Differential Transmission Line
F
IGURE
D
Zo = Ro + Rs
IAGRAM FOR
4. T
Rs
YPICAL
LVCMOS D
Zo = 50
LVDS D
10
require a matched load termination of 100
the receiver input.
resistance (Rs) equals the transmission line impedance. In
addition, matched termination at the crystal input will attenuate
the signal in half. This can be done in one of two ways. First,
R1 and R2 in parallel should equal the transmission line
impedance. For most 50 applications, R1 and R2 can be 100 .
This can also be accomplished by removing R1 and making R2
50 .
Reference Document: JEDEC Publication 95, MO-153
VCC
V
RIVER
DD
RIVER TO
R1
100
R1
R2
.1uf
T
ERMINATION
XTAL I
XTAL_IN
XTAL_OUT
+
-
NPUT
ICS844256BGI REV. A DECEMBER 21, 2007
2.5V or 3.3V
I
NTERFACE
across near