cs4341a Cirrus Logic, Inc., cs4341a Datasheet - Page 11

• Manufacturer Part Number: cs4341a
• Description: 24-bit, 192 Khz Stereo Dac With Volume Control
• Manufacturer: Cirrus Logic, Inc.

3.9
The control port is used to load all the internal register settings (see section 5). The operation of the control
port may be completely asynchronous with the audio sample rate. However, to avoid potential interference
problems, the control port pins should remain static if no operation is required.
The control port operates in one of two modes: I
Notes: MCLK must be applied during all I
DS582F2
Control Port Interface
When excess capacitive loading is present on the I
sufficient hysteresis to meet the standard I
mon I
Trigger buffer, a 74HC14 for example, on the SCL line just prior to the CS4341A. This will not
affect the operation of the I
3.9.2
The device has MAP (memory address pointer) auto increment capability enabled by the INCR bit
(also the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive I
or reads, and SPI writes. If INCR is set to 1, MAP will auto increment after each byte is written,
allowing block reads or writes of successive registers.
3.9.1
2
C configurations with a resistor pull-up. A workaround is achieved by placing a Schmitt
Rise Time for Control Port Clock
MAP Auto Increment
S C L
2
C bus as pin 6 is an input only.
Figure 6. I
2
V A
C communication.
2
2
C or SPI.
2
C Buffer Example
C rise time specification. This prevents the use of com-
2
C clock line, pin 6 (SCL/CCLK) may not have
P in 6
CS4341A
2
C writes
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