cs4228-ks Cirrus Logic, Inc., cs4228-ks Datasheet - Page 25

• Manufacturer Part Number: cs4228-ks
• Description: 24-bit, Surround Sound Codec
• Manufacturer: Cirrus Logic, Inc.

Serial Clock — SCLK
Left/Right Clock — LRCK
Digital Ground - DGND
Digital Power - VD
Digital Interface Power - VL
DS307PP1
Pin 5, Bidirectional
Function:
Pin 6, Bidirectional
Function:
Pin 7, Inputs
Function:
Pin 8, Input
Function:
Pin 9, Input
Function:
Clocks serial data into the SDIN1, SDIN2, and SDIN3 pins, and out of the SDOUT pin. The pin is an output
in master mode, and an input in slave mode.
In master mode, SCLK is configured as an output. MCLK is divided internally to generate SCLK at the
desired multiple of the sample rate.
In slave mode, SCLK is configured as an input. The serial clock can be provided externally, or the pin can
be grounded and the serial clock derived internally from MCLK.
The required relationship between the Left/Right clock, serial clock and serial audio data is defined by the
Serial Port Mode register. The options are detailed in Figures 9, 10, 11 and 12.
The Left/Right clock determines which channel is currently being input or output on the serial audio data
output, SDOUT. The frequency of the Left/Right clock must be at the output sample rate, Fs. In Master
mode, LRCK is an output, in Slave Mode, LRCK is an input whose frequency must be equal to Fs and
synchronous to the Master clock.
Audio samples in Left/Right pairs represent simultaneously sampled analog inputs whereas Right/Left
pairs will exhibit a one sample period difference. The required relationship between the Left/Right clock,
serial clock and serial data is defined by the Serial Port Mode register. The options are detailed in Figures
9, 10, 11 and 12.
Digital ground reference.
Digital power supply. Typically 3.3 VDC.
Digital interface power supply. Typically 3.3 or 5.0 VDC. All digital output voltages and input thresholds
scale with VL.
CS4228
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