S25FL040A Meet Spansion Inc., S25FL040A Datasheet - Page 21

• Manufacturer Part Number: S25FL040A
• Description: Small Sector For Boot And Parameter Storage 4-megabit Cmos 3.0 Volt Flash Memory With 50 Mhz Spi Bus Interface
• Manufacturer: Meet Spansion Inc.

9.7
July 2, 2007 S25FL040A_00_B2
Read Status Register (RDSR)
The Read Status Register (RDSR) command outputs the state of the Status Register bits.
the status register bits and their functions.
The RDSR command may be written at any time, even while a program, erase, or Write Status Register
operation is in progress. The host system should check the Write In Progress (WIP) bit before sending a new
command to the device if an operation is already in progress.
sequence, which also shows that it is possible to read the Status Register continuously until CS# is driven
high.
The following describes the status and control bits of the Status Register.
Write In Progress (WIP) bit: Indicates whether the device is busy performing a Write Status Register,
program, or erase operation. This bit is read-only, and is controlled internally by the device. If WIP is 1, one of
these operations is in progress; if WIP is 0, no such operation is in progress.
Write Enable Latch (WEL) bit: Determines whether the device will accept and execute a Write Status
Register, program, or erase command. When set to 1, the device accepts these commands; when set to 0,
the device rejects the commands. This bit is set to 1 by writing the WREN command, and set to 0 by the
WRDI command, and is also automatically reset to 0 after the completion of a Write Status Register, program,
or erase operation. WEL cannot be directly set by the WRSR command.
Block Protect (BP2, BP1, BP0) bits: Define the portion of the memory area that will be protected against
any changes to the stored data. The Write Status Register (WRSR) command controls these bits, which are
non-volatile. When one or more of these bits is set to 1, the corresponding memory area (see
SCK
CS#
SO
SI
Bit
7
6
5
4
3
2
1
0
Mode 3
Mode 0
Hi-Z
Status Register Bit
SRWD
WEL
BP2
BP1
BP0
WIP
0
—
—
1
Figure 9.7 Read Status Register (RDSR) Command Sequence
Command
2
D a t a
3
4
Status Register Write Disable
5
Write Enable Latch
Write in Progress
Table 9.3 S25FL040A Status Register
S h e e t
Bit Function
Block Protect
6
7
MSB
S25FL040A
—
—
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
8
Status Register Out
9
10
11
12
1 = Protects when W# is low
0 = No protection, even when W# is low
Not used
Not used
000–111 = Protects upper half of address range in 5 sizes. See
Table
1 = Device accepts Write Status Register, program, or erase
commands
0 = Ignores Write Status Register, program, or erase commands
1 = Device Busy. A Write Status Register, program, or erase
operation is in progress
0 = Ready. Device is in standby mode and can accept commands.
13
7.1.
14
Figure 9.7
15
MSB
shows the RDSR command
Status Register Out
Description
Table 9.3
Table 7.1
shows
21