S25FL128K Meet Spansion Inc., S25FL128K Datasheet - Page 21

• Manufacturer Part Number: S25FL128K
• Description: 128-mbit Cmos 3.0 Volt Flash Memory With 104-mhz Spi Serial Peripheral Interface Multi I/o Bus
• Manufacturer: Meet Spansion Inc.

April 1, 2011 S25FL128K_00_02
6.2.5
Write Status Register (01h)
complete and if the device can accept another instruction. The Status Register can be read continuously, as
shown in
The Write Status Register instruction allows the Status Register to be written. Only non-volatile Status
Register bits SRP0, SEC, TB, BP2, BP1, BP0 (bits 7 thru 2 of Status Register-1) and CMP, LB3, LB2, LB1,
QE, SRP1 (bits 14 thru 8 of Status Register-2) can be written to. All other Status Register bit locations are
read-only and will not be affected by the Write Status Register instruction. LB3-1 are non-volatile OTP bits;
once each is set to 1, it can not be cleared to 0. The Status Register bits are shown in
Figure 6.2 on page
To write non-volatile Status Register bits, a standard Write Enable (06h) instruction must previously have
been executed for the device to accept the Write Status Register Instruction (Status Register bit WEL must
equal 1). Once write enabled, the instruction is entered by driving CS# low, sending the instruction code
“01h”, and then writing the status register data byte as illustrated in
To write volatile Status Register bits, a Write Enable for Volatile Status Register (50h) instruction must have
been executed prior to the Write Status Register instruction (Status Register bit WEL remains 0). However,
SRP1 and LB3, LB2, LB1 can not be changed from “1” to “0” because of the OTP protection for these bits.
Upon power off, the volatile Status Register bit values will be lost, and the non-volatile Status Register bit
values will be restored when power on again.
To complete the Write Status Register instruction, the CS# pin must be driven high after the eighth or
sixteenth bit of data that is clocked in. If this is not done the Write Status Register instruction will not be
executed. If CS# is driven high after the eighth clock the CMP, QE and SRP1 bits will be cleared to 0.
During non-volatile Status Register write operation (06h combined with 01h), after CS# is driven high, the
self-timed Write Status Register cycle will commence for a time duration of t
Characteristics on page
instruction may still be accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the Write
Status Register cycle and a 0 when the cycle is finished and ready to accept other instructions again. After
the Write Status Register cycle has finished, the Write Enable Latch (WEL) bit in the Status Register will be
cleared to 0.
During volatile Status Register write operation (50h combined with 01h), after CS# is driven high, the Status
Register bits will be refreshed to the new values within the time period of t
Electrical Characteristics on page
Refer to
for all status Register bits are 0.
CLK
CS#
SO
SI
= MSB
Mode 3
Mode 0
Section 6.1, Status Register on page 13
Figure
D a t a
0
6.6. The instruction is completed by driving CS# high.
High Impedance
Instruction (05h or 35h)
15, and described
1
S h e e t
Figure 6.6 Read Status Register Instruction Sequence Diagram
2
54). While the Write Status Register cycle is in progress, the Read Status Register
3
4
54). BUSY bit will remain 0 during the Status Register bit refresh period.
( P r e l i m i n a r y )
5
6
Section 6.1, Status Register on page
S25FL128K
7
7
8
6
for detailed Status Register Bit descriptions. Factory default
9
Status Register 1 or 2 Out
5
10
4
11
3
12 13 14 15
2
1
Figure
0
SHSL2
7
16 17
6.7.
W
13.
Status Register 1 or 2 Out
6
(see
(see
5
18 19
Section 7.6, AC Electrical
4
Section 7.6, AC
Figure 6.1
3
20
2
21 22 23
1
and
0
7
21