isl6422b Intersil Corporation, isl6422b Datasheet - Page 9

• Manufacturer Part Number: isl6422b
• Description: Dual Output Lnb Supply And Control Voltage Regulator With I2c Interface For Advanced Satellite Set-top Box Designs
• Manufacturer: Intersil Corporation

Functional Pin Description
TDOUT1, TDOUT2
PGND1, PGND2
ADDR0, ADDR1
EXTM1, EXTM2
TCAP1, TCAP2
GATE1, GATE2
TDIN1, TDIN2,
VSW1, VSW2
TXT1, TXT2
SELVTOP1,
SELVTOP2
CS1, CS2
VO1, VO2
SYMBOL
CPVOUT
BYPASS
SGND
SDA
VCC
SCL
FLT
Input of the linear post-regulator.
Dedicated ground for the output gate driver of respective PWM.
Bypass capacitor for internal 5V.
These pins can be used in two ways :
Bidirectional data from/to I
Clock from I
Current sense input; connect the sense resistor R
Small signal ground for the IC.
Capacitor for setting rise and fall time of the output of LNB A and LNB B respectively. Typical value is 0.15µF.
TXT1 and TXT2 are the Tone Transmit signal inputs used to change the tone decoder threshold. The threshold is 200mV max
for the Rx mode. The TXT1, TXT2 are set low and the threshold is 400mV min in the Tx mode when TXT1, TXT2 are set high.
Main power supply to the chip.
These are the gate drive outputs of PWM A and PWM B respectively. These high current driver outputs are capable of driving
the gate of a power FET. These outputs are actively held low when V
Output voltage for LNB A and LNB B respectively.
Address pins select four different device addresses per Table 19.
1) As an input for externally modulated DiSEqC tone signal which is transfered to the symetrically onto V
2) Alternatively apply a DiSEqC modulation envelope which modulates an internal tone and then transfers it symetrically onto
V
This is an open drain output from the controller. When the FLT goes low it indicates that an Over-Temperature, Over Load
Fault, UVLO, or a condition causing I
actual cause of the error. A high on the FLT indicates that the device is functioning normally.
Charge pump decoupling capacitor is to be connected to this pin.
When this pin is low, the V
When this pin is high, the 18.3V/19.3V range is selected by the I
The voltage select pin voltage VSPEN1, VSPEN2 I
Setting VSPEN1, VSPEN2 high disables these pins and voltage selection will be done using the I
VTOP1, VTOP2 only.
TDIN1, TDIN2 are the tone decoder inputs for Channels 1 and 2. TDOUT1, TDOUT2 are the tone detector outputs for Channels
1 and 2. TDOUT1, TDOUT2 are open drain outputs.
OUT
2
9
C bus.
2
OUT
C bus.
is in the 13.3V/14.3V range selected by the I
2
C to reset has occured. The processor should then look at the I
ISL6422B
SC
2
C bit must be set low for the SELVTOP1, SELVTOP2 pins to be active.
at this pin for desired overcurrent value for respective PWM.
FUNCTION
2
C bit VTOP1 and VTOP2.
CC
is below the UVLO threshold.
2
C bit VBOT1 and VBOT2.
2
C bits VBOT1, VBOT2 and
2
C register to get the
OUT
August 10, 2007
FN6486.1