isl6422b Intersil Corporation, isl6422b Datasheet - Page 12

• Manufacturer Part Number: isl6422b
• Description: Dual Output Lnb Supply And Control Voltage Regulator With I2c Interface For Advanced Satellite Set-top Box Designs
• Manufacturer: Intersil Corporation

START
SDA
SCL
The STOP condition is a LOW to HIGH transition on the SDA
line while SCL is HIGH. A STOP condition must be sent
before each START condition.
Byte Format
Every byte put on the SDA line must be eight bits long. The
number of bytes that can be transmitted per transfer is
unrestricted. Each byte has to be followed by an
acknowledge bit. Data is transferred with the most significant
bit first (MSB).
Acknowledge
The master (microprocessor) puts a resistive HIGH level on
the SDA line during the acknowledge clock pulse (Figure 6).
The peripheral that acknowledges has to pull-down (LOW)
the SDA line during the acknowledge clock pulse so that the
SDA line is stable LOW during this clock pulse (of course,
set-up and hold times must also be taken into account).
The peripheral which has been addressed has to generate
an acknowledge after the reception of each byte, otherwise
the SDA line remains at the HIGH level during the ninth
clock pulse time. In this case, the master transmitter can
generate the STOP information in order to abort the transfer.
The ISL6422B will not generate the acknowledge if the
POWER OK signal from the UVLO is LOW.
Transmission Without Acknowledge
Avoiding detection of the acknowledgement, the
microprocessor can use a simpler transmission; it waits one
clock without checking the slave acknowledging, and sends
the new data. Although, this approach is less protected from
error and decreases the noise immunity.
SDA
SCL
CONDITION
START
S
FIGURE 6. ACKNOWLEDGE ON THE I
FIGURE 5. START AND STOP WAVEFORMS
MSB
1
2
12
8
2
C BUS
ACKNOWLEDGE
FROM SLAVE
CONDITION
STOP
P
9
ISL6422B
ISL6422B Software Description
Interface Protocol
The interface protocol is comprised of the following, as
shown below in Table 2:
• A start condition (S)
• A chip address byte (MSB on left; the LSB bit determines
• A sequence of data (1 byte + Acknowledge)
• A stop condition (P)
System Register Format
All bits reset to 0 at Power-On
NOTE: X = Bit not used
SR3H SR3M SR3L
SR7H SR7M SR7L
• R, W = Read and Write bit
• R = Read-only bit
S 0 0 0 1 0 0 0 R/W ACK
R, W
R, W
SR1H SR1M
SR4H SR4M
SR5H SR5M
SR8H SR8M
SR2H
SR6H
R, W
R, W
R, W
R, W
R, W
R, W
read (1) or write (0) transmission) (the assigned I
address for the ISL6422B is 0001 00XX)
R, W
R, W
SR2M
SR6M
R, W
R, W
R, W
R, W
R, W
R, W
TABLE 10. CONTROL REGISTER 8 (SR8)
TABLE 5. COMMAND REGISTER 3 (SR3)
TABLE 9. COMMAND REGISTER 7 (SR7)
TABLE 6. CONTROL REGISTER 4 (SR4)
TABLE 7. STATUS REGISTER 5 (SR5)
TABLE 3. STATUS REGISTER 1 (SR1)
TABLE 4. TONE REGISTER 2 (SR2)
TABLE 8. TONE REGISTER 6 (SR6)
TABLE 2. INTERFACE PROTOCOL
R, W
R, W
SR1L
SR2L
SR4L
SR5L
SR6L
SR8L
R, W
R, W
R, W
R, W
R, W
R, W
DCL1 VSPEN1 ISEL1R ISEL1H ISEL1L
DCL2 VSPEN2 ISEL2R ISEL2H ISEL2L
R, W
R, W
ENT1
ENT2 MSEL2 TTH2
R, W
R, W
R, W
R, W
OTF
EN1
EN2
R
X
X
R, W
R, W
CABF1 OUVF1 OLF1
CABF2 OUVF2 OLF2
MSEL1 TTH1
R, W
R, W
R, W
R, W
R
R
X
X
Data (8 bits)
R, W
R, W
R, W
R, W
R, W
R, W
X
R
X
R
VTOP1 VBOT1
VTOP2 VBOT2
R, W
R, W
R, W
R, W
R, W
R, W
R
R
X
X
August 10, 2007
2
C slave
ACK P
FN6486.1
BCF1
BCF2
R, W
R, W
R, W
R, W
R, W
R, W
R
X
R
X