isl6334d Intersil Corporation, isl6334d Datasheet - Page 24

• Manufacturer Part Number: isl6334d
• Description: Vr11.1, 4-phase Pwm Controller With Phase Dropping, Droop Disabled And Load Current Monitoring Features
• Manufacturer: Intersil Corporation

higher if desired. Choosing f
cause problems with too much phase shift below the system
bandwidth.
In the solutions to the compensation equations, there is a
single degree of freedom. For the solutions presented in
Equation 29, R
The remaining compensation components are then selected.
In Equation 29, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent-series resistance of
the bulk output-filter capacitance; and V
peak-to-peak sawtooth signal amplitude, typically 1.5V.
Output Filter Design
The output inductors and the output capacitor bank together
to form a low-pass filter responsible for smoothing the
pulsating voltage at the phase nodes. The output filter also
must provide the transient energy until the regulator can
respond. Because it has a low bandwidth compared to the
switching frequency, the output filter necessarily limits the
system transient response. The output capacitor must
supply or sink load current while the current in the output
inductors increases or decreases to meet the demand.
In high-speed converters, the output capacitor bank is usually
the most costly (and often the largest) part of the circuit.
Output filter design begins with minimizing the cost of this part
of the circuit. The critical load parameters in choosing the
output capacitors are the maximum size of the load step, ΔI;
the load-current slew rate, di/dt; and the maximum allowable
output-voltage deviation under transient loading, ΔV
Capacitors are characterized according to their capacitance,
ESR, and ESL (equivalent series inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will initially
deviate by an amount approximated by the voltage drop across
the ESL. As the load current increases, the voltage drop across
the ESR increases linearly until the load current reaches its final
R
C
C
R
C
1
1
2
C
C
=
=
=
=
=
R
------------------------------------------- -
---------------------------------------------------------------------------------------------------- -
(
---------------------------------------------------------------------------------------- -
---------------------------------------------------------------------------------------------------- -
(
V
2 π
2 π
FB
L C
PP
⋅
⋅
⋅
V
⋅
IN
)
⋅
)
V
R
2
------------------------------------------- -
2
–
⎛
⎝
IN
2π
L C
FB
⋅
⋅
⋅
C ESR
f
(
f
⋅
0
2 π f
0
FB
⋅
⎞
⎠
C ESR
⋅
⋅
(
2
⋅
⋅
2 π f
f
⋅
f
–
HF
⋅
HF
can be arbitrarily chosen as 1kΩ to 2kΩ.
⋅
f
C ESR
⋅
0
⋅
HF
⋅
⋅
⋅
⋅
V
(
f
(
HF
IN
HF
⋅
L C
L C
⋅
⋅
⋅
⋅
L C
L C R
⋅
HF
⋅
) R
L C
) R
24
⋅
⋅
⋅
–
⋅
to be lower than 10f
1
FB
FB
–
)
1
FB
⋅
)
⋅
V
V
P-P
P-P
P-P
is the
MAX
0
(EQ. 29)
can
.
ISL6334D
value. The capacitors selected must have sufficiently low ESL
and ESR so that the total output-voltage deviation is less than
the allowable maximum. Neglecting the contribution of inductor
current and regulator response, the output voltage initially
deviates by an amount, as shown in Equation 30:
The filter capacitor must have sufficiently low ESL and ESR
so that ΔV < ΔV
Most capacitor solutions rely on a mixture of high-frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
The ESR of the bulk capacitors also creates the majority of
the output-voltage ripple. As the bulk capacitors sink and
source the inductor AC ripple current (see “Interleaving” on
page 10 and Equation 2), a voltage develops across the
bulk-capacitor ESR equal to I
output capacitors are selected, the maximum allowable
ripple voltage, V
inductance, as shown in Equation 31.
Since the capacitors are supplying a decreasing portion of
the load current while the regulator recovers from the
transient, the capacitor voltage becomes slightly depleted.
The output inductors must be capable of assuming the entire
load current before the output voltage decreases more than
ΔV
Equation 32 gives the upper limit on L for the cases when
the trailing edge of the current transient causes a greater
output-voltage deviation than the leading edge. Equation 33
addresses the leading edge. Normally, the trailing edge
dictates the selection of L because duty cycles are usually
less than 50%. Nevertheless, both inequalities should be
evaluated, and L should be selected based on the lower of
the two results. In each equation, L is the per-channel
inductance, C is the total output capacitance, and N is the
number of active channels.
V
L
L
L
≈
≤
≤
≥
MAX
(
2NCV
-------------------- - ΔV
(
------------------------- - ΔV
ESL
1.25
(
(
ESR
ΔI
(
ΔI
. This places an upper limit on inductance.
)
2
) NC
)
)
O
2
---- -
dt
di
)
⎛
⎝
----------------------------------------------------------- -
+
V
IN
(
f
ESR
S
MAX
MAX
V
–
PP(MAX)
MAX
IN
N V
) ΔI
V
–
.
OUT
PP MAX
ΔI ESR
–
ΔI ESR
(
(
(
⎞ V
⎠
, determines the lower limit on the
OUT
)
)
C,PP
)
⎛
⎝
V
IN
(ESR). Thus, once the
–
V
O
⎞
⎠
October 29, 2008
(EQ. 30)
(EQ. 31)
(EQ. 32)
(EQ. 33)
FN6802.0