isl6341a Intersil Corporation, isl6341a Datasheet - Page 9

• Manufacturer Part Number: isl6341a
• Description: 5v Or 12v Single Synchronous Buck Pulse-width Modulation Pwm Controller
• Manufacturer: Intersil Corporation

minimum should be nominally 9.6ms and the maximum
14.4ms. If the short condition is finally removed, the output
should ramp up normally on the next t2 cycle.
Starting up into a shorted load looks the same as a retry into
that same shorted load. In both cases, OCP is always
enabled during soft-start; once it trips, it will go into retry
(hiccup) mode. The retry cycle will always have two dummy
time-outs, plus whatever fraction of the real soft-start time
passes before the detection and shut-off; at that point, the
logic immediately starts a new two dummy cycle time-out.
OVERCURRENT EQUATIONS
For both the ISL6341, ISL6341B and ISL6341A, the
overcurrent function will trip at a peak inductor current
(I
where I
typical). The OC trip point varies in a system mainly due to
the MOSFET’s r
temperature). To avoid overcurrent tripping in the normal
operating load range, find the R
Equation 1 with:
For an equation for the ripple current see “Output Inductor
Selection” on page 14.
The range of allowable voltages detected (I
is 0mV to 550mV; but the practical range for typical
MOSFETs is smaller. If the voltage drop across R
set too low, that can cause almost continuous OCP tripping
and latch-off. It would also be very sensitive to system noise
and in-rush current spikes, so it should be avoided. The
maximum setting is 550mV, but most of the recommended
I
PEAK
1. The maximum r
2. The minimum I
3. Determine I
GND>
PEAK)
temperature.
where ΔI is the output inductor ripple current.
FIGURE 6. OCP RETRY OPERATION (ISL6341A ONLY)
=
OCSET
determined by Equation 1:
t0
I
-------------------------------------------------
OCSET
4.8ms
r
DS ON
INTERNAL SOFT-START RAMP
is the internal OCSET current source (10μA
PEAK
DS(ON)
xR
(
OCSET
OCSET
DS(ON)
)
for
t1
variations (over process, current and
I
PEAK
from the specification table.
4.8ms
at the highest junction
9
OCSET
>
I
OUT MAX
0ms TO 4.8ms
t2
(
resistor from
(0.5V/DIV)
OCSET
V
)
ISL6341, ISL6341A, ISL6341B
OUT
+
t0
(
--------- -
ΔI
2
)
4.8ms
OCSET
*R
,
OCSET
(EQ. 1)
is
)
MOSFETs for the ISL6341, ISL6341A, ISL6341B are not
expected to handle the power of the maximum trip point. Any
voltage setting above 600mV will clamp to the maximum
setting. No resistor at all should give the clamped maximum
value (unless the loading on the LGATE prevents charging
the node fully). However, a resistor (>60k) is recommended;
there is no low-voltage clamp on LGATE, so it could rise to
over 3V and turn-on for 4ms during the sampling; that could
discharge a pre-biased output.
There is no way to disable the OCP, but setting it to the
maximum value may be far enough above the normal
expected range.
Note that conditions during power-up may look different than
normal operation. For example, during power-up in a 12V
system, the IC starts operation just above 4V; if the supply
ramp is slow, the soft-start ramp might be over well before
12V is reached. So with lower gate drive voltages, the
r
effectively lowering the OCP trip. In addition, the ripple
current will likely be different at lower input voltage.
Another factor is the digital nature of the soft-start ramp. On
each discrete voltage step, there is in effect a small load
transient and a current spike to charge the output capacitors.
The height of the current spike is not controlled; it is affected
by the step size of the output, the value of the output
capacitors, as well as the IC error amp compensation. So it
is possible to trip the overcurrent with in-rush current, in
addition to the normal load and ripple considerations.
OCP is always enabled during soft-start, so there is
protection starting up into a shorted load.
Undervoltage Protection
The output is protected against undervoltage conditions by
monitoring the VOS pin. An external resistor divider (similar
ratio to the one on the FB pin) makes the voltage equal the
0.8V internal reference under normal operation. If the output
goes too low (25% below 0.8V = 0.6V nominal on VOS), the
output will latch off, with UGATE and LGATE both forced low.
This requires toggling V
(toggling COMP/EN will NOT restart it). The UV protection is
not enabled until the end of the soft-start ramp (as shown in
Figure 2).
Figure 7 shows a case where V
down to the 75% point; both gate drivers stop switching, and
the V
load, at a rate determine by the conditions, and the output
components.
DS(ON)
OUT
of the MOSFETs will be higher during power-up,
is pulled low by the disturbance, as well as the
CC
(power-down and up) to restart
OUT
(and thus VOS) is pulled
August 20, 2007
FN6538.0