isl6341a Intersil Corporation, isl6341a Datasheet - Page 8

• Manufacturer Part Number: isl6341a
• Description: 5v Or 12v Single Synchronous Buck Pulse-width Modulation Pwm Controller
• Manufacturer: Intersil Corporation

The actual monitoring of the lower MOSFET’s ON-resistance
starts 200ns (nominal) after the edge of the internal PWM logic
signal (that creates the rising external LGATE signal). This is
done to allow the gate transition noise and ringing on the
PHASE pin to settle out before monitoring. The monitoring
ends when the internal PWM edge (and thus LGATE) goes low.
The OCP can be detected anywhere within the above window.
To allow sufficient time to detect OCP, the regulator will limit
the maximum UGATE duty cycle to ~85% at 300kHz (~75%
at 600kHz); there will always be an LGATE pulse of at least
300ns. This minimum width will also act as a boot-refresh
function. If the boot capacitor loses any charge while UGATE
is high, it will be refreshed each cycle while LGATE is high.
The ISL6341, ISL6341B and ISL6341A share most of the
detection circuitry; the main difference between them is what
happens after detection.
ISL6341, ISL6341B
When overcurrent is detected (while LGATE is high), the logic
will disable UGATE, and leave LGATE high until the current
drops to 1/2 of its programmed OCP value. This may take
several clock cycles, and it keeps the current from building up
too high. Once the current is low enough, UGATE will go high
on the next PWM cycle, and OCP will be monitored when
LGATE goes high. If OCP trips a 2nd time, it will again wait
until the current drops. If it trips again the 3rd time, it will latch
off the output (LGATE and UGATE low). If there is no OCP trip
on one of the retries, then the trip-counter resets to zero, and
three new consecutive cycles are required to latch off.
Figure 4 shows a typical waveform for the ISL6341,
ISL6341B, where the normal inductor current is around 10A,
and the OCP trip is 16A. This is just an illustration; the actual
shape of the waveforms depends on the component values,
as well as the characteristics of the load and the short. On the
third trip, the gate drivers stop switching, and the current goes
to zero. To recover from this latched off condition, the user
must toggle V
toggle COMP/EN pin to restart (either includes initialization
and soft-start).
1/2 OC
GND>
GND>
0A>
OC
FIGURE 4. OCP TIMING (ISL6341, ISL6341B ONLY)
I
INDUCTOR
UGATE (24V/DIV)
LGATE (12V/DIV)
CC
(power-down and up) for a new POR, or
(10A/DIV)
8
ISL6341, ISL6341A, ISL6341B
As the output inductor current rises and falls, the output
voltage is also affected. Note that in extreme cases during
the three consecutive trips, the UV may actually trip before
the OCP. The IC provides protection in either case, but
perhaps not quite at the programmed current. An OCP trip
can be reset by toggling either POR or COMP/EN, but a UV
trip is only reset by toggling POR. See Table 2 for the
protection summary.
Starting up into a shorted load will be handled the same way;
but the waveforms may look different, since the output is not
yet at its final value. OCP is always enabled during soft-start
(UV is not); it will need the three consecutive trips to latch off.
ISL6341A
Figure 5 shows the same conditions for the ISL6341A. For
this version, when overcurrent is first detected (while LGATE
is high), the logic will shut off the output (LGATE and UGATE
both go low), and the current goes to zero.
It will then go into a “hiccup” mode of infinite retries. After two
dummy soft-start time-outs, a real soft-start will begin. If the
short is still there, it will trip during the soft-start ramp, and
will start another retry cycle. Once the short is removed, the
next real soft-start will be successful, and normal operation
can continue.
Figure 6 shows the ISL6341A output response during a retry
of an output shorted to GND. At time t0, the output has been
turned off, due to sensing an overcurrent condition. There
are two internal soft-start delay cycles (t1 and t2) to allow the
MOSFETs to cool down, to keep the average power
dissipation in retry at an acceptable level. At time t2, the
output starts a normal soft-start cycle, and the output tries to
ramp. If the short is still applied, and the current reaches the
OCSET trip point any time during soft-start ramp period, the
output will shut off and return to time t0 for another delay
cycle. The retry period is thus two dummy soft-start cycles
plus one variable one, which depends on how long it takes to
trip the sensor each time. Figure 6 shows an example where
the output gets about half-way up before shutting down;
therefore, the retry (or hiccup) time will be around 12ms. The
GND>
GND>
0A>
OC
I
INDUCTOR
FIGURE 5. OCP TIMING (ISL6341A ONLY)
LGATE (12V/DIV)
UGATE (24V/DIV)
(10A/DIV)
August 20, 2007
FN6538.0