isl9106 Intersil Corporation, isl9106 Datasheet - Page 9

• Manufacturer Part Number: isl9106
• Description: 1.2a 1.6mhz Low Quiescent Current High Efficiency Synchronous Buck Regulator
• Manufacturer: Intersil Corporation

Block Diagram
Theory of Operation
The ISL9106 is a step-down switching regulator optimized
for battery-powered handheld applications. The regulator
operates at typical 1.6MHz fixed switching frequency under
heavy load condition to allow small external inductor and
capacitors to be used for minimal printed-circuit board (PCB)
area. At light load, the regulator can be selected to enter skip
mode to reduce the switching frequency, unless forced to the
fixed frequency, to minimize the switching loss and to
maximize the battery life. The quiescent current under skip
mode with no loading is typically only 17μA. The supply
current is typically only 0.1μA when the regulator is disabled.
PWM Control Scheme
The ISL9106 uses the peak-current-mode pulse-width
modulation (PWM) control scheme for fast transient
response and pulse-by-pulse current limiting. Figure 24
shows the circuit functional block diagram. The current loop
consists of the oscillator, the PWM comparator COMP,
FB
PG
RSI
EN
SHUTDOWN
BANDGAP
VREF5
VREF4
VREF3
9
PGOOD
DELAY
START
+
+
SOFT-
+
0.8V
SCP
SLOPE
COMP
+
EAMP
FIGURE 24. FUNCTIONAL BLOCK DIAGRAM
+
+
COMP
ISL9106
OSCILLATOR
current sensing circuit, and the slope compensation for the
current loop stability. The current sensing circuit consists of
the resistance of the P-Channel MOSFET when it is turned
on and the Current Sense Amplifier (CSA). The control
reference for the current loops comes from the Error
Amplifier (EAMP) of the voltage loop.
The PWM operation is initialized by the clock from the
oscillator. The P-Channel MOSFET is turned on at the
beginning of a PWM cycle and the current in the P-Channel
MOSFET starts ramping up. When the sum of the CSA
output and the compensation slope reaches the control
reference of the current loop, the PWM comparator COMP
sends a signal to the PWM logic to turn off the P-Channel
MOSFET and to turn on the N-Channel MOSFET. The
N-MOSFET remains on till the end of the PWM cycle. Figure 25
shows the typical operating waveforms during the normal PWM
operation. The dotted lines illustrate the sum of the slope
compensation ramp and the CSA output.
SKIP
OCP
+
+
CONTROLLER
PROTECTION
MODE
PWM/PFM
DRIVER
VREF2
VREF1
LOGIC
ZERO-CROSS
SENSING
SHUTDOWN
CSA
+ +
VIN
SW
PGND
SGND
June 29, 2007
FN6509.0