isl9444 Intersil Corporation, isl9444 Datasheet - Page 16

• Manufacturer Part Number: isl9444
• Manufacturer: Intersil Corporation

Functional Description
General Description
The ISL9444 integrates control circuits for three synchronous
buck converters. The three synchronous bucks operate out-
of-phase to substantially reduce the input ripple and thus reduce
the input filter requirements.
Each part has 3 independent enable/disable control lines
(EN/SS1, EN2 and EN3), which provide flexible power-up
sequencing. The soft-start time is programmable individually by
adjusting the soft-start capacitors connected from EN/SS1,
TK/SS2 and TK/SS3, respectively.
The valley current mode control scheme with input voltage
feed-forward ramp simplifies loop compensation and provides
excellent rejection to input voltage variation.
Input Voltage Range
The ISL9444 is designed to operate from input supplies ranging
from 4.5V to 28V.
The input voltage range can be effectively limited by the
available minimum PWM off time.
V
where,
V
path, including the lower FET, inductor and PC board.
V
upper FET, inductor and PC board resistances.
The maximum input voltage and minimum output voltage is
limited by the minimum on-time (t
V
Where t
Internal 5V Linear Regulator (VCC_5V) and
External VCC Bias Supply (EXTBIAS)
All ISL9444 functions can be internally powered from an on-chip,
low dropout 5V regulator or an external 5V bias voltage via the
EXTBIAS pin. Bypass the linear regulator’s output (VCC_5V) with a
4.7µF capacitor to the power ground. The ISL9444 also employs
an undervoltage lockout circuit which disables all regulators
when VCC_5V falls below 3.6V.
The internal LDO can source over 75mA to supply the IC, power
the low side gate drivers and charge the boot capacitors. When
driving large FETs at high switching frequency, little or no
regulator current may be available for external loads.
For example, a single large FET with 15nC total gate charge
requires 15nC x 300kHz = 4.5mA (15nC x 600kHz = 9mA). Also,
at higher input voltages with larger FETs, the power dissipation
across the internal 5V will increase. Excessive dissipation across
this regulator must be avoided to prevent junction temperature
rise. Thermal protection may be triggered if die temperature
increases above +150°C due to excessive power dissipation.
IN min
IN max
d1
d2
(
(
= sum of the voltage drops in the charging path, including the
= sum of the parasitic voltage drops in the inductor discharge
)
)
ON(min)
≤
=
V
⎛
⎜
⎝
OUT
-----------------------------------------------------------------------
1 t
–
= 100ns.
x
OFF min
⎛
⎜
⎝
----------------------------------------------------------- -
t
ON min
V
(
OUT
(
)
+
)
×
V
×
V
Frequency
OUT
d1
Frequency
16
ON(min)
⎞
⎟
⎠
⎞
⎟
⎠
+
V
).
d2
–
V
d1
(EQ. 2)
(EQ. 3)
ISL9444
When large MOSFETs are used, an external 5V bias voltage can
be applied to EXTBIAS pin to alleviate excessive power
dissipation. Voltage at the EXTBIAS pin must always be lower
than the voltage at the VIN pin to prevent biasing of the power
stage through EXTBIAS and VCC_5V. An external UVLO circuit
might be necessary to guarantee smooth soft-starting.
The internal LDO has an overcurrent limit of typically 150mA. For
better efficiency, connect VCC_5V to VIN for 5V ±10% input
applications.
Enable Signals and Soft-Start Operation
Typical applications for the ISL9444 use programmable analog
soft-start or the TK/SSx pins for tracking. The soft-start time can
be set by the value of the soft-start capacitors connected from
the EN/SS1 for PWM1 to ground and from TK/SSx pins to ground
for PWM2 and PWM3. Inrush current during start-up can be
alleviated by adjusting the soft-starting time.
After the VCC_5V pin reaches the UVLO threshold, the ISL9444
PWM1 soft-start circuitry becomes active. The internal 1.55µA
charge current begins charging up the soft-start capacitor
connected from the EN/SS1 pin to GND. The PWM1 output
remains inactive until voltage on the EN/SS1 pin reaches 1.3V.
As the voltage on the EN/SS1 pin rises from 1.3V to 2V, the
PWM1 reference voltage is clamped to the voltage on the
EN/SS1 pin minus 1.3V. PWM1 output voltage thus rises from 0V
to regulation as EN/SS1 rises from 1.3V to 2V. Charging of the
soft-start capacitor continues until the voltage on the EN/SS1 pin
reaches 3.5V.
Power sequencing can be achieved by using the PGOODx and
ENx pins. When the ENx pin is pulled high, the internal 1.55µA
charge current begins charging up the soft-start capacitor
connected from the TK/SSx pin to GND. The respective reference
voltage is clamped to the voltage on the TK/SSx pin. Thus, PWM2
and PWM3 output voltages ramp from 0V to regulation as
voltage on TK/SS2 and TK/SS3 goes up from 0V to 0.7V.
Charging of the soft-start capacitors continues until the voltage
on the TK/SSx reaches 3.5V.
The typical soft-start time is set according to Equation 4:
For PWM2 and PWM3, when the soft-starting time set by
external C
circuit of 2ms takes over the soft-start. There is no internal
soft-start for PWM1.
PGOODx will toggle to high when the corresponding output is up
and in regulation.
Pulling the ENx low disables the corresponding PWM channel.
The TK/SSx pin will also be discharged to GND by internal
MOSFETs.
Output Voltage Programming
The ISL9444 provides a precision internal reference voltage to
set the output voltage. Based on this internal reference, the
output voltage can thus be set from 0.7V up to a level
determined by the input voltage, the maximum duty cycle, and
the conversion efficiency of the circuit.
t
SSx
=
0.7V
SS
⎛
⎝
or tracking is less than 2ms, an internal soft-start
------------------- -
1.55μA
C
SSx
⎞
⎠
May 23, 2011
FN7665.0
(EQ. 4)