isl3873a Intersil Corporation, isl3873a Datasheet - Page 31

• Manufacturer Part Number: isl3873a
• Description: Wireless Lan Integrated Medium Access Controller With Baseband Processor
• Manufacturer: Intersil Corporation

Control Registers
The following tables describe the function of each control register along with the associated bits in each control register.
Write to control, Read to verify control, setup while TX_PE and RX_PE are low
Bit 7:4
Bit 3:0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bits 7:1
Bit 0
Bits 0 - 7
Bits 0 - 7
CONFIGURATION REGISTER 3 ADDRESS (06h) R/W TX PREAMBLE LENGTH FOR SHORT PREAMBLE
CONFIGURATION REGISTER 4 ADDRESS (08h) R/W TX PREAMBLE LENGTH FOR LONG PREAMBLE
Part Code
3 = HFA3863 series
Version Code
0 = 3863 Version
This register is used to define the phase of clocks and other interface signals. 00h is normal setting.
This control bit selects the phase of the receive carrier rotation sense.
Logic 1 = Inverted rotation (CW), Invert Q in.
Logic 0 = normal rotation (CCW).
This control bit selects the phase of the transmit carrier rotation sense.
Logic 1 = Inverted rotation (CW), Invert Q out.
Logic 0 = normal rotation (CCW).
This control bit selects the phase of the transmit output clock (TXCLK) pin.
Logic 1 = Inverted TXCLK.
Logic 0 = NON-Inverted TXCLK.
This control bit selects the active level of the Transmit Ready (TX_RDY) output which is an output pin at the test port, pin.
Logic 1 = TX_RDY Active 0.
Logic 0 = TX_RDY Active 1.
This control bit selects the active level of the transmit enable (TX_PE) input pin.
Logic 1 = TX_PE Active 0.
Logic 0 = TX_PE Active 1.
This control bit selects the active level of the Clear Channel Assessment (CCA) output pin.
Logic 1 = CCA Active 1.
Logic 0 = CCA Active 0.
This control bit selects the active level of the MD_RDY output pin.
Logic 1 = MD_RDY is Active 0.
Logic 0 = MD_RDY is Active 1.
This controls the phase of the RX_CLK output.
Logic 1 = Invert Clk.
Logic 0 = Non-Inverted Clk.
Reserved.
Initialization.
0 = Normal Operation.
1 = Soft Initialization of learned behavior registers such as DCoffset, NoiseFloor, FAR, RecPacketsNOcs1, and
RecPacketsUSEdef. Holds AGC logic reset. At part initialization, must be set, then after CR47 is loaded, cleared.
This register contains the count for the Preamble length counter for short preambles selected by CR5 bit 3. Setup while TX_PE
is low. For IEEE 802.11 use38h. For other than IEEE 802.11 applications, in general increasing the preamble length will improve
low signal to noise acquisition performance at the cost of greater link overhead. The minimum suggested value is 56d = 38h. A 2
symbol TX power amplifier ramp up is added to programmed value.
This register contains the count for the Preamble length counter for long preambles selected with CR5 bit 3 or CR11 bit 4.
Setup while TX_PE is low. For IEEE 802.11 use 80h. For other than IEEE 802.11 applications, in general increasing the preamble
length will improve low signal to noise acquisition performance at the cost of greater link overhead. The minimum suggested value
is 56d = 38h. A 2 symbol TX power amplifier ramp up is added to programmed value. If you program 128 you get 130.
CONFIGURATION REGISTER 0 ADDRESS (0h) R PART/VERSION CODE
CONFIGURATION REGISTER 2 ADDRESS (04h) R/W RX CONFIGURE
CONFIGURATION REGISTER 1 ADDRESS (02h) R/W I/O POLARITY