isl12008 Intersil Corporation, isl12008 Datasheet - Page 12

• Manufacturer Part Number: isl12008
• Description: I2c Real Time Clock With Battery Backup
• Manufacturer: Intersil Corporation

is also used as the OF bit for M41T00S compatibility, and the
two OF bits are interchangable.
Analog Trimming Register (ATR) [Address 0Ah]
ANALOG TRIMMING REGISTER (ATR<5:0>)
Six analog trimming bits, ATR0 to ATR5, are provided in
order to adjust the on-chip load capacitance value for
frequency compensation of the RTC. Each bit has a different
weight for capacitance adjustment. For example, using a
Citizen CFS-206 crystal with different ATR bit combinations
provides an estimated ppm adjustment range from -34ppm
to +80ppm to the nominal frequency compensation. The
combination of analog and digital trimming can give up to
-97.0695ppm to +206.139ppm of total adjustment.
The effective on-chip series load capacitance, C
ranges from 9pF to 40.5pF with a mid-scale value of 12.5pF
(default). C
capacitors, C
pins to ground (see Figure 9). The value of C
given in Equation 1:
The effective series load capacitance is the combination of
C
where b5 is ATR5 bit, b4 is ATR4 bit, b3 is ATR3 bit, b2 is
ATR1 bit, and b0 is ATR0 bit.
For example, C
(ATR = 100000b [32d]) = 4.5pF and C
[31d]) = 20.25pF. The entire range for the series combination
0Ah
Default
C
C
C LOAD
ADDR
X1
X
LOAD
=
and C
(
16
TABLE 5. ANALOG TRIMMING REGISTER (ATR)
BMATR1 BMATR0 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0
=
=
⋅
⎛
⎝
---------------------------------- -
⎛
⎝
b
---------- -
C
16 b5
----------------------------------------------------------------------------------------------------------------------------- -
X2
5
7
0
LOAD
1
X1
+
⋅
X1
in Equation 2:
X1
X2
8
1
+
LOAD
⋅
FIGURE 9. DIAGRAM OF ATR
and C
b
---------- -
C
+
is changed via two digitally controlled
4
1
8 b4
X2
+
⋅
6
0
⎞
⎠
C
C
4 b3
(ATR = 000000b [0d]) = 12.5pF, C
X1
X2
⋅
X2
+
4 b3
, connected from the X1 and X2
+
⋅
2 b2
5
0
⋅
12
+
2 b2
2
+
⋅
1 b1
4
0
OSCILLATOR
⋅
CRYSTAL
+
1 b1
LOAD
+
⋅
3
0
0.5 b0
+
⋅
0.5 b
(ATR = 011111b
X1
2
0
+
⋅
and C
9
LOAD
0 9
)pF
+
1
0
⎞ pF
⎠
X2
,
(EQ. 2)
(EQ. 1)
LOAD
are
0
0
ISL12008
of load capacitance goes from 4.5pF to 20.25pF in 0.25pF
steps. Note that these are typical values.
BATTERY MODE ATR SELECTION (BMATR <1:0>)
Since the accuracy of the crystal oscillator is dependent on
the V
capability to adjust the capacitance between V
when the device switches between power sources.
Digital Trimming Register (DTR) [Address 07h]
DIGITAL TRIMMING REGISTER (DTR<5:0>)
Six digital trimming bits, DTR0 to DTR5, are provided to
adjust the average number of counts per second and
average the ppm error to achieve better accuracy.
• DTR5 is a sign bit. DTR5 = “0” means frequency
• DTR<4:0> are scale bits. With DTR5 = “0”, DTR<4:0>
A range from -63.0696ppm to +126.139ppm can be
represented by using these 3 bits.
For example, with DTR = 11111, the digital adjustment is
(1111b[15d]*4.0690) = +126.139ppm. With DTR = 01111, the
digital adjustment is (-(1111b[15d]*2.0345)) = -63.0696ppm.
512HZ FREQUENCY OUTPUT ENABLE BIT (FT)
This bit enables/disables the 512Hz frequency output on the
FT/OUT pin. When the FT is set to “1”, the FT/OUT pin
outputs the 512Hz frequency, regardless of the Digital Output
selection bit (OUT). The 512Hz frequency output is used for
crystal compensation with ATR and DTR registers. When the
FT is set to “0”, the 512Hz frequency is disabled and the
function of FT/OUT pin is selected by the Digital Output
selection bit (OUT). The FT bit is set to “0” on power-up. The
FT/OUT pin is an open drain output requires the use of a
pull-up resistor.
07h
Default
ADDR
compensation is < 0. DTR5 = “1” means frequency
compensation is > 0.
gives -2.0345ppm adjustment per step. With DTR5 = “1”,
DTR<4:0> gives +4.0690ppm adjustment per step.
DD
BMATR1
/V
TABLE 6. DIGITAL TRIMMING REGISTER (DTR)
0
0
1
1
OUT
BAT
7
0
operation, the ISL12008 provides the
FT
6
0
BMATR0
DTR5 DTR4 DTR3 DTR2 DTR1 DTR0
0
1
0
1
5
0
4
0
0pF
-0.5pF (≈ +2ppm)
+0.5pF (≈ -2ppm)
+1pF (≈ -4ppm)
3
0
(C
CAPACITANCE
BAT
DELTA
2
0
September 26, 2008
DD
TO C
and V
VDD
1
0
FN6690.1
)
BAT
0
0