isl706xrheval1z Intersil Corporation, isl706xrheval1z Datasheet - Page 10

• Manufacturer Part Number: isl706xrheval1z
• Description: Rad-hard, 5.0v/3.3v µ-processor Supervisory Circuits
• Manufacturer: Intersil Corporation

Functional Overview
The ISL705xRH and ISL706xRH provide the functions needed for
monitoring critical voltages in high reliability applications such as
microprocessor systems. Functions of the these supervisors include
power-on reset control; supply voltage supervisions; power-fail
detection; manual-reset assertion and a watch dog timer. The
integration of all these functions along with their high threshold
accuracy, low power consumption, and radiation tolerance make
these devices ideal for critical supply monitoring.
Reset Output
Reset control has long been a critical aspect of embedded
control design. Microprocessors require a reset signal during
power up to ensure that the system environment is stable before
initialization.
The reset signal provides several benefits:
• It prevents the system microprocessor from starting to operate
• It prevents the processor from operating prior to stabilization
• It ensures that the monitored device is held out of operation
• It allows time for an FPGA to perform its self configuration
On power-up, once V
low. As V
threshold (V
(typ). RST pulses low whenever V
Figure 3). If a brownout condition occurs in the middle of a
previously initiated reset pulse, the pulse is lengthened 200ms
(typ).
On power-down, once V
stays low and is guaranteed to be low until V
The ISL705BRH and ISL706BRH active-high RST output is simply
the complement of the RST output, and is guaranteed to be valid
with V
active-low open-drain reset output is functionally identical to RST.
Power Failure Monitor
Besides monitoring V
Power-Failure Monitor feature that supervises an additional
critical voltage on the Power-Fail Input (PFI) pin. For example, the
PFI pin could be used to provide an early power-fail warning,
overvoltage detection or monitor a power supply other than V
PFO goes low whenever PFI is less than V
The threshold detector can be adjusted using an external resistor
divider network to provide custom voltage monitoring for
voltages greater than V
Figure 14).
VIN
with insufficient voltage.
of the oscillator.
until internal registers are initialized.
prior to initialization of the circuit.
DD
=
ISL705ARH, ISL705BRH, ISL705CRH, ISL706ARH, ISL706BRH, ISL706CRH
V
DD
down to 1.2V. The ISL705CRH and ISL706CRH
PFI
RST
rises, RST stays low. When V
⎛
⎝
R1
--------------------- -
), an internal timer releases RST after 200ms
R2
+
R2
DD
⎞
⎠
DD
PFI
DD
reaches 1.2V, RST is guaranteed logic
for reset control, these devices have a
, according to Equation 1 (see
falls below the reset threshold, RST
10
DD
degrades to below V
DD
PFI
DD
rises above the reset
.
drops below 1.2V.
RST
(EQ. 1)
(see
DD
.
Manual Reset
The manual reset input (MR) allows designers to add manual
system reset capability via a push button switch (see Figure 15).
The MR input is an active low debounced input which asserts
reset if the MR pin is pulled low to less than V
150ns. After MR is released, the reset output remains asserted
for t
so it can be driven by external logic. By connecting WDO to MR,
one can force a watchdog time out to generate a reset pulse.
Watch Dog Timer
The watchdog time circuit checks for coherent program
execution by monitoring the WDI pin. If the processor does not
toggle the watchdog input within t
low. As long as reset is asserted or the WDI pin is tri-stated, the
watchdog timer will stay cleared and not count. As soon as reset
is released and WDI is driven high or low, the timer will start
counting. Pulses as short as 50ns can be detected on the
ISL705xRH, on ISL706xRH pulses as short as 100ns can be
detected.
Whenever there is a low-voltage V
Unlike the reset outputs, however, WDO goes high as soon as
V
open or connected to a tri-stated high impedance input, the
Watchdog Timer is disabled and only pulls low when V
Applications Information
Negative Voltage Sensing
This family of devices can be used to sense and monitor the
presence of both a positive and negative rail. V
monitors the positive supply while PFI monitors the negative rail.
PFO is high when the negative rail degrades below a V
and remains low when the negative rail is above the V
As the differential voltage across the R1, R2 divider is increased,
the resistor values must be chosen such that the PFI node is
<1.25V when the -V supply is satisfactory and the positive supply
DD
RST
FIGURE 15. CONNECTING A MANUAL RESET PUSH-BUTTON
FIGURE 14. CUSTOM V
rises above its voltage trip point (see Figure 4). With WDI
and then released. MR is a TTL/CMOS logic compatible,
V
IN
ISL705xRH/ISL706xRH
R
1
R
2
TH
WITH RESISTOR DIVIDER ON PFI
20k
MR
DD
WD
PFI
ISL705xRH/ISL706xRH
condition, WDO goes low.
(1.0s min), WDO will go
IL
DD
PB
for at least
is used to
December 1, 2011
trip
DD
TRIP
FN7662.1
< V
value.
value
RST
.