sc26c198a1a NXP Semiconductors, sc26c198a1a Datasheet
sc26c198a1a
Related parts for sc26c198a1a
sc26c198a1a Summary of contents
Page 1
... COS etc.) and, for transmitters or 347 receivers, the fill level of the FIFO. 348 348 The Octal UART provides a power down mode in which the 348 oscillator is stopped but the register contents are maintained. This 349 results in reduced power consumption of several orders of 351 magnitudes ...
Page 2
... TTL input levels. Outputs switch between full V High speed CMOS technology 68 pin PLCC 10% CC Commercial Commercial Industrial Industrial + + + +85 C SC26C198C1A SC26C198A1A SC68C198C1A SC68C198A1A V = 3.3V 10% CC Commercial Industrial + +85 C SC26L198C1A SC26L198A1A SC68L198C1A SC68L198A1A 337 ...
Page 3
... Philips Semiconductors Octal UART with TTL compatibility at 3.3V and 5V supply voltages PIN CONFIGURATIONS PINOUT Pin Function CEN 4 W_RN DACKN 9 I/O0a 10 I/O1a 11 RxDa 12 RxDb 13 I/O2a 14 I/O3a 15 TxDa 16 I/O0b 17 I/O1b 18 I/O2b 19 I/O3b 20 TxDb 21 I/O0c 22 Vss 23 I/O1c 24 I/O2c 25 I/O3c ...
Page 4
... I/O Input/Output 0: Multi–use input or output pin for the UART. I/O1(a–d) I/O Input/Output 1: Multi–use input or output pin for the UART. I/O2(a–d) I/O Input/Output 2: Multi–use input or output pin for the UART. I/O3(a–d) I/O Input/Output 3: Multi–use input or output pin for the UART. G (1:0) I Global general purpose inputs, available to any/all channels. ...
Page 5
... C4. Addressing of the various functions of the OCTART is through the address bus A(7:0). The 26C198 is compatible with the SC28L194 Quad UART in software and function. A[7 general sense, is used to separate the data portion of the circuit from the control portion. Asynchronous bus cycle The asynchronous mode requires one bus cycle of the chip select (CEN) for each read or write to the chip ...
Page 6
... OCTART and from there to the host. See the description of the ”UART channel” under detailed descriptions below. Character Recognition Character recognition is specific to each of the eight UARTs. Three programmable characters are provided for the character recognition for each channel. The three are general purpose in nature and may be set to only cause an interrupt or to initiate some rather complex operations specific to ” ...
Page 7
... The global registers and the CIR update procedure are further described in the Interrupt Arbitration system I/O Ports Each of the eight UART blocks contains an I/O section of four ports. These ports function as a general purpose post section which services the particular UART they are associated with. External clocks are input and internal clocks are output through these ports ...
Page 8
... Philips Semiconductors Octal UART with TTL compatibility at 3.3V and 5V supply voltages loaded into the TxFIFO while the transmitter is disabled, hence it is necessary to enable the transmitter and then load the TxFIFO not possible to load the TxFIFO and then enable the transmission. Note the difference between transmitter disable and transmitter reset ...
Page 9
... SR[4], will be set upon receipt of the start bit of the new (overrunning) character. I/O ports Each of the eight UARTs includes four I/O ports equipped with ”change of state” detectors. The pins are individually programmable for an input only function or one of three output functions. These functions are controlled by the ”I/O Port Configuration Register (I/OPCR)) They will normally be used for the RTSN– ...
Page 10
... COS detectors. General Purpose Pins In addition to the I/O ports for each UART four other ports are provided which service the entire chip. Two are dedicated as inputs and one as an output. The G 1 and G 0 are the input pins ...
Page 11
... IACKN (or the ”Update CIR” command) was asserted. The Octal UART will respond to the IACKN cycle with an interrupt vector. The interrupt vector may be a fixed value, the content of the Interrupt Vector Register, or ,when ”Interrupt Vector Modification is enabled via ICR, it may contain codes for the interrupt type and/or interrupting channel ...
Page 12
... There is a single arbiter interrupt number that is not associated with any of the UART channels the ”Threshold Value” and is comprised of 7 bits from the Interrupt Control Register, ICR, and three zeros in the channel field only when one or more of the enabled interrupt sources generates a arbitration value larger than the threshold value that the IRQN will be asserted ...
Page 13
... These modes could be invoked in all of the major modes.. However it may not be reasonable in many situations. Watch-dog Timer Time–out Mode Each receiver in the Octal UART is equipped with a watch-dog timer that is enabled by the ”Watch-dog Timer Enable Register (WTER). The watch-dog ”barks” (times out counts of the receiver clock (64 bit times) elapse with no RxFIFO activity ...
Page 14
... Xon/Xoff Operation Receiver Mode Since the receiving FIFO resources in the Octal UART are limited, some means of controlling a remote transmitter is desirable in order to lessen the probability of receiver overrun. The Octal UART provides two methods of controlling the data flow. A hardware assisted means of accomplishing control, the so– ...
Page 15
... MR0(3:2)=’00’ and enabling the Xon/Xoff interrupt in the IMR. The Octal UART can present the Xon/Xoff recognition event to the interrupt arbiter for IRQN generation. The IRQN generation may be masked by setting bit 4 of the Interrupt Mask Register, IMR. The bid level of an Xon/Xoff recognition event is controlled by the Bidding Control Register X, BCRX, of the channel ...
Page 16
... Controls the operation of the host interface logic. If reset, the power on/reset default, the host interface can accommodate arbitrarily long bus I/O cycles. If the bit is set, the Octal UART expects four Sclk cycle bus I/O operations similar to those produced by an i80386 processor in non–pipelined mode. The major differences in these modes are observed in the DACKN pin function ...
Page 17
... Philips (Signets)’ UART families where the RTSN function triggered on FIFO full. This behavior caused problems with PC UARTs that could not stop transmission at the proper time. . The RTSN feature can be used to prevent overrun in the receiver, by using the RTSN output signal, to control the CTSN input of the transmitting device ...
Page 18
... Octal UART with TTL compatibility at 3.3V and 5V supply voltages MR2[7:6] – Mode Select The Octal UART can operate in one of four modes: MR2[7:6] = b’00 is the normal mode, with the transmitter and receiver operating independently. MR2[7:6] = b’01 places the channel in the automatic echo mode, which automatically re transmits the received data ...
Page 19
... BRG – 3600 01100 BRG – 4800 01101 BRG – 7200 01110 BRG – 9600 01111 BRG – 14.4K Table 8. CR – Command Register CR is used to write commands to the Octal UART. Bits 7:3 Bit 2 Bit 1 Channel Lock TxD and Command codes see RxFIFO Enable Tx “ ...
Page 20
... Reserved 11110 Resets all UART channel registers. This command provides a means to zero all the UART channels that are not reset to x’ reset command or a hardware reset. 11111 Reserved for channels b-h, for channel a: executes a chip wide reset. Executing this command in channel a is equivalent to a hardware reset with the RESETN pin ...
Page 21
... Philips Semiconductors Octal UART with TTL compatibility at 3.3V and 5V supply voltages Table 9. Command Register Code Commands x’12, x13, x’14, x’15, x’1f (marked with*) are global and exist only in channel A’s register space. Channel Command Channel Code Command CR[7:3] Description 00000 NOP 00001 Reserved ...
Page 22
... Time–out This register provides the status of all potential interrupt sources for a UART channel. When generating an interrupt arbitration value, the contents of this register are masked by the interrupt mask register (IMR bit in the ISR is a ’1’ and the corresponding bit in the IMR is also a ’ ...
Page 23
... Philips Semiconductors Octal UART with TTL compatibility at 3.3V and 5V supply voltages IMR[7] – Controls if a change of state in the inputs equipped with input change detectors will cause an interrupt. IMR[6] – Controls the generation of an interrupt by the watch-dog timer event. If set, a count of 64 idle bit times in the receiver will begin interrupt arbitration. IMR[5] – ...
Page 24
... Philips Semiconductors Octal UART with TTL compatibility at 3.3V and 5V supply voltages Table 22. XISR – Xon–Xoff Interrupt Status Register Bits 7:6 Received X Character Automatic X Character Status transmission status 00 – none 00 – none 01 – Xoff received 01 – Xon transmitted 10 – Xon received 10 – Xoff transmitted 11 – ...
Page 25
... GIBCR) The Current Interrupt Register is provided to speed up the specification of the interrupting condition in the Octal UART. The CIR is updated at the beginning of an interrupt acknowledge bus cycle or in response to an Update CIR command. (see immediately above) Although interrupt arbitration continues in the background, the current interrupt information remains frozen in the CIR until another IACKN cycle or Update CIR command occurs ...
Page 26
... Philips Semiconductors Octal UART with TTL compatibility at 3.3V and 5V supply voltages Table 33. Global Interrupting Type Register Bit 7:6 Receiver Interrupt Transmitter Interrupt 0x – not receiver 0 – not transmitter 10 – with receive errors 1 – transmitter interrupt 11 – w/o receive errors A register associated with the interrupting channel as defined in the CIR. It contains the type of interrupt code for all interrupts. Table 34. GRxFIFO – ...
Page 27
... Philips Semiconductors Octal UART with TTL compatibility at 3.3V and 5V supply voltages clocking mechanism that will allow the pin to change synchronously with an internal or external stimulus. See diagram below. Table 39. GPOSR – General Purpose Output Select Register GPOSR selects the signal or data source for the G and Rx clock selection is straight forward ...
Page 28
... The ”Register Map Summary” shows the configuration of the lower four bits of the address that is the same for the individual UARTs. It also shows the addresses for the several in the address space of UART A and REGISTER MAP SUMMARY Table 43 ...
Page 29
... Global Interrupt Byte Count 1001 1111 (x9F) Global Interrupt Type Register REGISTER MAP DETAIL Table 45. Register Map, Control NOTE: The register maps for channels A and B (UARTs A and B) contain some control registers that configure the entire chip. These are denoted by a symbol A(7:0) A(7:0) ...
Page 30
... Philips Semiconductors Octal UART with TTL compatibility at 3.3V and 5V supply voltages A(7:0) A(7:0) 0001 0000 (x10) Mode Register 0 MR0b 0001 0001 (x11) Mode Register 1 MR1b 0001 0010 (x12) I/O Port Configuration Reg b I/OPCRb 0001 0011 (x13) 0001 0100 (x14) 0001 0101 (x15) 0001 0110 (x16) ...
Page 31
... Philips Semiconductors Octal UART with TTL compatibility at 3.3V and 5V supply voltages A(7:0) A(7:0) 0011 0000 (x30) Mode Register 0 MR0d 0011 0001 (x31) Mode Register 1 MR1d 0011 0010 (x32) I/O Port Configuration Reg d I/OPCRd 0011 0011 (x33) 0011 0100 (x34) 0011 0101 (x35) 0011 0110 (x36) ...
Page 32
... Philips Semiconductors Octal UART with TTL compatibility at 3.3V and 5V supply voltages 01010000 (x50) Mode Register 0 MR0f 01010001 (x51) Mode Register 1 MR1f 01010010 (x52) I/OPort Configuration Reg f I/OPCRf 01010011 (x53) 01010100 (x54) 01010101 (x55) 01010110 (x56) 01010111 (x57) 01011000 (x58) Xon Character Reg f (XonCRf) ...
Page 33
... Philips Semiconductors Octal UART with TTL compatibility at 3.3V and 5V supply voltages 01110000 (x70) Mode Register 0 MR0h 01110001 (x71) Mode Register 1 MR1h 01110010 (x72) I/OPort Configuration Reg h I/OPCRh 01110011 (x73) 01110100 (x74) 01110101 (x75) 01110110 (x76) 01110111 (x77) 01111000 (x78) Xon Character Reg h (XonCRh) ...
Page 34
... Philips Semiconductors Octal UART with TTL compatibility at 3.3V and 5V supply voltages Table 46. Register Map, Data A(7:0) A(7:0) 1000 0000 (x80) Mode Register a (MR2a) 1000 0001 (x81) Status Register a (SRa) 1000 0010 (x82) Interrupt Status Register a (ISRa) 1000 0011 (x83) Receiver FIFO Reg a (RxFIFOa) 1000 0100 (x84) ...
Page 35
... Philips Semiconductors Octal UART with TTL compatibility at 3.3V and 5V supply voltages A(7:0) A(7:0) 1010 0000 (xA0) Mode Register c (MR2c) 1010 0001 (xA1) Status Register c (SRc) 1010 0010 (xA2) Interrupt Status Register c (ISRc) 1010 0011 (xA3) Receiver FIFO Reg c (RxFIFOc) 1010 0100 (xA4) Input Port Reg c (IPRc) ...
Page 36
... Philips Semiconductors Octal UART with TTL compatibility at 3.3V and 5V supply voltages A(7:0) 11000000 (xC0) Mode Register e (MR2e) 11000001 (xC1) Status Register e (SRe) 11000010 (xC2) Interrupt Status Register e (ISRe) 11000011 (xC3) Receiver FIFO Reg e (RxFIFOe) 11000100 (xC4) Input Port Reg e (IPRe) 11000101 (xC5) I/O Port Interrupt and Output e (I/OPIORe) ...
Page 37
... Philips Semiconductors Octal UART with TTL compatibility at 3.3V and 5V supply voltages A(7:0) 11100000 (xE0) Mode Register g (MR2g) 11100001 (xE1) Status Register g (SRg) 11100010 (xE2) Interrupt Status Register g (ISRg) 11100011 (xE3) Receiver FIFO Reg g (RxFIFOg) 11100100 (xE4) Input Port Reg g (IPRg) 11100101 (xE5) I/O Port Interrupt and Output g (I/OPIORg) ...
Page 38
... Philips Semiconductors Octal UART with TTL compatibility at 3.3V and 5V supply voltages Limitations: Minimum RESETN pin pulse width is 10 SClk cycles after Vcc reaches operational range DC ELECTRICAL SPECIFICATIONS (26C198 and 68C198 5.0V 10 SYMBOL SYMBOL PARAMETER PARAMETER V Input low voltage IL Input high voltage (except X1/CLK) ...
Page 39
... Philips Semiconductors Octal UART with TTL compatibility at 3.3V and 5V supply voltages AC ELECTRICAL CHARACTERISTICS SYMBOL SYMBOL FIGURE FIGURE RESET TIMING t RESET pulse width RES BUS TIMING t A0-A7 setup time before Sclk C3 rising edge AS t A0-A7 hold time after Sclk C3 rising edge AH CEN setup time before Sclk C1 high (ASYNC) ...
Page 40
... Philips Semiconductors Octal UART with TTL compatibility at 3.3V and 5V supply voltages AC ELECTRICAL CHARACTERISTICS (26C198 and 68C198) SYMBOL SYMBOL FIGURE FIGURE COMMUNICATION CRYSTAL CLOCK Fx1 X1 clock frequency Low / High time T/RFx1 X1 Rise / Fall time COUNTER / TIMER BAUD RATE CLOCK (EXTERNAL CLOCK INPUT) ...
Page 41
... Philips Semiconductors Octal UART with TTL compatibility at 3.3V and 5V supply voltages DC ELECTRICAL SPECIFICATIONS (26L198 and 68L198 3 SYMBOL SYMBOL PARAMETER PARAMETER V Input low voltage IL Input high voltage (except X1/CLK Input high voltage (X1/CLK Output low voltage (except OD outputs) ...
Page 42
... Philips Semiconductors Octal UART with TTL compatibility at 3.3V and 5V supply voltages AC ELECTRICAL CHARACTERISTICS SYMBOL SYMBOL FIGURE FIGURE RESET TIMING t RESET pulse width RES BUS TIMING t A0-A7 setup time before Sclk C3 rising edge AS t A0-A7 hold time after Sclk C3 rising edge AH CEN setup time before Sclk C1 high (ASYNC) ...
Page 43
... Philips Semiconductors Octal UART with TTL compatibility at 3.3V and 5V supply voltages AC ELECTRICAL CHARACTERISTICS SYMBOL SYMBOL FIGURE FIGURE COMMUNICATION CRYSTAL CLOCK Fx1 X1 clock frequency Low / High time T/RFx1 X1 Rise / Fall time COUNTER / TIMER BAUD RATE CLOCK (EXTERNAL CLOCK INPUT) FC/T Clock frequency ...
Page 44
... Philips Semiconductors Octal UART with TTL compatibility at 3.3V and 5V supply voltages C1 SCLK CEN W_RN ADDRESS INVALID DATA DACKN SCLK CEN W_RN ADDRESS INVALID DATA DACKN 1995 May RWH VALID INVALID RWS Figure 2. Basic Write Cycle, ASYNC t CS ...
Page 45
... Philips Semiconductors Octal UART with TTL compatibility at 3.3V and 5V supply voltages C1 SCLK CEN W_RN ADDRESS INVALID DATA DACKN SCLK CEN W_RN ADDRESS INVALID DATA DACKN 1995 May RWH VALID INVALID DATA= RWS Figure 4. Basic Read Cycle, ASYNC ...
Page 46
... Philips Semiconductors Octal UART with TTL compatibility at 3.3V and 5V supply voltages C1 SCLK IACKN CEN W_RN INVALID ADDRESS DATA DACKN t CS NOTE: CEN must not be active during an IACKN cycle. If CEN is active, IACKN will be ignored and a normal read or write will be executed according to W_RN. In the synchronous mode, extended IACKN signal will start another IACKN ...
Page 47
... Philips Semiconductors Octal UART with TTL compatibility at 3.3V and 5V supply voltages T/RF T/RF Figure 9. Counter/Timer Baud Rate Clock, External 1X DATA CLOCK Note: CEN must not be active during an IACKN cycle. If CEN is active IACKN will be ignored and a normal read or write will be executed according to W_RN. 1995 May 1 ...
Page 48
... Philips Semiconductors Octal UART with TTL compatibility at 3.3V and 5V supply voltages INDEX Numbers 1x and 16x modes, Receiver, 342 1x and 16x modes, Transmitter, 342 A Address Recognition Character Register, 357 ARCR, 357 Asynchronous bus cycle, 339 B Baud Rate Generator , 340 BCRA, 357 BCRBRK, 357 ...
Page 49
... Philips Semiconductors Octal UART with TTL compatibility at 3.3V and 5V supply voltages T Timing Circuits, 340 Transmitter, 341 Transmitter FIFO, 342, 357 Tx, Status Bits , 341 TxCSR , 352 TxEMT, 341 TxFIFO, 357 TxRDY, 341 U UCIR, 359 Update CIR, 345, 359 W Wake Up Mode, 347 1995 May 1 ...