si2200 Silicon Laboratories, si2200 Datasheet - Page 18

• Manufacturer Part Number: si2200
• Description: Rf Synthesizer With Integrated Vcos Integrated Vcos - Silicon Laboratories
• Manufacturer: Silicon Laboratories

Si2200
2.4. Output Frequencies
The IF and RF output frequencies are set by
programming the R- and N-Divider registers. Each PLL
has its own R and N registers so that each can be
programmed independently. Programming either the R-
or N-Divider register for RF1 or RF2 automatically
selects the associated output.
When XINDIV2 = 0, the reference frequency on the XIN
pin is divided by R, and this signal is the input to the
PLL’s phase detector. The other input to the phase
detector is the PLL’s VCO output frequency divided by
2N for the RF PLLs or N for the IF PLL. After an initial
transient:
Equation 1. f
PLLs)
Equation 2. f
The integers R are set by programming the RF1 R-
Divider register (Register 6), the RF2 R-Divider register
(Register 7) and the IF R-Divider register (Register 8).
The integers N are set by programming the RF1 N-
Divider register (register 3), the RF2 N-Divider register
(Register 4), and the IF N-Divider register (Register 5).
If the optional divide-by-2 circuit on the XIN pin is
enabled (XINDIV2 = 1), after an initial transient:
Each N-Divider is implemented as a conventional high-
speed divider. That is, it consists of a dual-modulus
prescaler, a swallow counter, and a lower speed
synchronous counter. However, the control of these
sub-circuits
appropriate N value should be programmed.
2.5. PLL Loop Dynamics
The transient response for each PLL is determined by
its phase detector update rate f (equal to f
the phase detector gain programmed for each RF1,
RF2, or IF synthesizer. (See Register 1.) Four different
settings for the phase detector gain are available for
each PLL. The highest gain is programmed by setting
the two phase detector gain bits to 00 and the lowest by
setting the bits to 11. The values of the available gains,
relative to the highest gain, are listed in Table 7.
18
f
f
OUT
OUT
Table 7. Gain Values (Register 1)
= (N/R)
= (N/2R)
is
K
OUT
OUT
P
00
01
Bits
handled
= (2N/R)
= (N/R)


f
REF
f
REF
(for the RF PLLs)

automatically.
(for the IF PLL).

f
Relative P.D.
REF
f
REF
Gain
1/2
(for the IF PLL).
1
(for the RF
REF
Only
/R) and
the
Rev. 1.0
In general, a higher phase detector gain will decrease
in-band phase noise and increase the speed of the PLL
transient until the point at which stability begins to be
compromised. The optimal gain depends on N. Table 8
lists recommended settings for different values of N.
The VCO gain and loop filter characteristics are not
programmable.
The settling time for each PLL is directly proportional to
its phase detector update period T (T equals 1/f ).
During the first 13 update periods, the Si2200 executes
the self-tuning algorithm. Thereafter, the PLL controls
the
architecture of the Si2200 PLLs, the time required to
settle the output frequency to 0.1 ppm error is only
about 25 update periods. Thus, the total time after
power-up or a change in programmed frequency until
the synthesized frequency is well settled—including
time for self-tuning—is around 40 update periods.
Note: This settling time analysis holds for f
2.6. RF and IF Outputs (RFOUT and IFOUT)
The RFOUT and IFOUT pins are driven by amplifiers
that buffer the RF VCOs and IF VCO, respectively. The
RF output amplifier receives its input from either the
RF1 or RF2 VCO, depending upon which R- or N-
Divider register was last written. For example,
programming
automatically selects the RF1 VCO output.
8192 to 16383
2048 to 4095
4096 to 8191
output
16384
f
100 s as specified in Table 5.
2047
N
Table 7. Gain Values (Register 1)
500 kHz
Table 8. Optimal K
frequency.
K
P
the
10
11
Bits
, the settling time can be a maximum of
K
P1
RF1
N-Divider
00
00
01
10
11
<1:0>
Because
Relative P.D.
K
P
P2
Gain
Settings
RF2
register
00
01
10
1/4
1/8
11
11
<1:0>
of
500 kHz
the
K
for
PI
<1:0>
00
01
10
11
11
IF
unique
. For
RF1