74ABT16823ADGG,118 NXP Semiconductors, 74ABT16823ADGG,118 Datasheet - Page 2

• Manufacturer Part Number: 74ABT16823ADGG,118
• Description: IC 18BIT INTRFC F-F 3ST 56TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74ABTr
• Type: D-Type Busr

Specifications of 74ABT16823ADGG,118

• Function: Master Reset
• Output Type: Tri-State Non Inverted
• Number Of Elements: 2
• Number Of Bits Per Element: 9
• Frequency - Clock: 190MHz
• Delay Time - Propagation: 2.3ns
• Trigger Type: Positive Edge
• Current - Output High, Low: 32mA, 64mA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74ABT16823ADG-T; 74ABT16823ADG-T; 935203280118

FEATURES
QUICK REFERENCE DATA
ORDERING INFORMATION
T
PIN DESCRIPTION
Philips Semiconductors
amb
Type number
74ABT16823ADL
74ABT16823ADGG
2004 Feb 02
Two sets of high speed parallel registers with positive
edge-triggered D-type flip-flops
Ideal where high speed, light loading, or increased fan-in are
required with MOS microprocessors
Live insertion/extraction permitted
Power-up 3-State
Power-up Reset
Output capability: +64 mA/–32 mA
Latch-up protection exceeds 500 mA per Jedec Std 17
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
SYMBOL
= –40 C to +85 C
54, 52, 51, 49, 48, 47, 45, 44, 43
42, 41, 40, 38, 37, 36, 34, 33, 31
15, 16, 17, 19, 20, 21, 23, 24, 26
C
I
t
t
I
C
PLH
PHL
CCZ
CCL
OUT
4, 11, 18, 25, 32, 39, 46, 53
3, 5, 6, 8, 9, 10, 12, 13, 14
IN
PIN NUMBER
7, 22, 35, 50
56, 29
55, 30
2, 27
1, 28
Propagation delay
nCP to nQx
Input capacitance
Output capacitance
Quiescent supply current
Quiescent su
Package
Name
SSOP56
TSSOP56
PARAMETER
ly current
Description
plastic shrink small outline package; 56 leads; body width 7.5 mm
plastic thin shrink small outline package; 56 leads; body width 6.1 mm
1MR, 2MR
1OE, 2OE
1CE, 2CE
SYMBOL
1CP, 2CP
1Q0-1Q8
2Q0-2Q8
1D0-1D8
2D0-2D8
GND
V
CC
C
V
V
Outputs disabled; V
Outputs low; V
I
O
L
= 0 V or V
= 50 pF; V
= 0 V or V
2
T
eliminate the extra packages required to buffer existing registers and
The registers are fully edge-triggered. The state of each D input, one
Enable (nCE) and Master Reset (nMR) which are ideal for parity bus
DESCRIPTION
The 74ABT16823A 18-bit bus interface register is designed to
provide extra data width for wider data/address paths of buses
carrying parity.
The 74ABT16823A has two 9-bit wide buffered registers with Clock
interfacing in high microprogrammed systems.
set-up time before the LOW-to-HIGH clock transition is transferred
to the corresponding flip-flop’s Q output.
amb
CONDITIONS
= 25 C; GND = 0 V
CC
CC
CC
CC
; 3-State
= 5 V
Output enable input (active-LOW)
Data inputs
Data outputs
Clock pulse input (active rising edge)
Clock enable input (active-LOW)
Master reset input (active-LOW)
Ground (0 V)
Positive supply voltage
= 5.5 V
CC
= 5.5 V
FUNCTION
74ABT16823A
TYPICAL
500
2.3
1.9
4
6
9
Version
SOT371-1
SOT364-1
Product data
UNIT
mA
pF
pF
ns
A