74LVC574ABQ,115 NXP Semiconductors, 74LVC574ABQ,115 Datasheet - Page 9

• Manufacturer Part Number: 74LVC574ABQ,115
• Description: IC OCT D FF POSEDG TRIG 20DHVQFN
• Manufacturer: NXP Semiconductors
• Series: 74LVCr
• Type: D-Type Busr

Specifications of 74LVC574ABQ,115

• Package / Case: 20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
• Function: Standard
• Output Type: Tri-State Non Inverted
• Number Of Elements: 1
• Number Of Bits Per Element: 8
• Delay Time - Propagation: 9ns
• Trigger Type: Positive Edge
• Current - Output High, Low: 24mA, 24mA
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Circuits: 1
• Logic Family: LVC
• Logic Type: D-Type Edge Triggered Flip-Flop
• Polarity: Non-Inverting
• Input Type: Single-Ended
• Propagation Delay Time: 3.2 ns at 3.3 V
• High Level Output Current: - 24 mA
• Supply Voltage (max): 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Voltage (min): 1.2 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency - Clock: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 74LVC574ABQ-G; 74LVC574ABQ-G; 935273517115

Philips Semiconductors
AC CHARACTERISTICS
GND = 0 V; t
Notes
1. All typical values are measured at T
2. These typical values are measured at V
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed
2004 Mar 22
SYMBOL
T
t
t
t
t
t
t
f
t
T
t
t
t
t
t
t
f
t
PHL
PZH
PHZ
W
su
h
max
sk(0)
PHL
PZH
PHZ
W
su
h
max
sk(0)
amb
amb
Octal D-type flip-flop with 5 V tolerant
inputs/outputs; positive edge-trigger; 3-state
by design.
/t
/t
/t
/t
/t
/t
PLH
PLH
PZL
PLZ
PZL
PLZ
= 40 to +85 C; note 1
= 40 to +125 C
r
= t
propagation delay CP to Qn
3-state output enable time
OE to Qn
3-state output disable time
OE to Qn
clock pulse width
HIGH or LOW
set-up time Dn to CP
hold time Dn to CP
maximum clock frequency
skew
propagation delay CP to Qn
3-state output enable time
OE to Qn
3-state output disable time
OE to Qn
clock pulse width
HIGH or LOW
set-up time Dn to CP
hold time Dn to CP
maximum clock frequency
skew
f
2.5 ns; C
PARAMETER
L
= 50 pF; R
amb
L
= 500 .
= 25 C.
CC
see Figs 7 and 10
see Figs 9 and 10
see Figs 9 and 10
see Fig.7
see Fig.8
see Fig.8
note 3
see Figs 7 and 10
see Figs 9 and 10
see Figs 9 and 10
see Fig.7
see Fig.8
see Fig.8
note 3
= 3.3 V.
WAVEFORMS
TEST CONDITIONS
9
2.7
3.0 to 3.6
2.7
3.0 to 3.6
2.7
3.0 to 3.6
2.7
3.0 to 3.6
2.7
3.0 to 3.6
2.7
3.0 to 3.6
2.7
3.0 to 3.6
3.0 to 3.6
2.7
3.0 to 3.6
2.7
3.0 to 3.6
2.7
3.0 to 3.6
2.7
3.0 to 3.6
2.7
3.0 to 3.6
2.7
3.0 to 3.6
2.7
3.0 to 3.6
3.0 to 3.6
V
CC
(V)
1.5
1.5
1.5
1.5
1.5
1.5
3.3
3.4
2.0
2.0
1.5
1.5
80
100
MIN.
3.6
3.2
4.3
3.5
2.8
2.5
1.7
0.3
150
0.2
TYP.
(2)
(2)
(2)
(2)
(2)
(2)
(2)
Product specification
74LVC574A
8.0
7.0
8.5
7.5
6.5
6.0
1.0
10.0
9.0
11.0
9.5
8.5
7.5
MAX.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
ns
UNIT