si3068 Silicon Laboratories, si3068 Datasheet - Page 31

• Manufacturer Part Number: si3068
• Description: Fcc+ Embedded Direct Access Arrangement
• Manufacturer: Silicon Laboratories

DAA Register 22. Ring Validation Control 1
Reset settings = 1001_0110
Bit
7:6
5:0
Name
Type
Bit
RDLY[1:0]
RMX[5:0]
Name
D7
RDLY[1:0]
R/W
Ring Delay.
These bits, in combination with the RDLY[2] bit, set the amount of time between when a
ring signal is validated and when a valid ring signal is indicated.
RDLY[2]
Ring Assertion Maximum Count.
These bits set the maximum ring frequency for a valid ring signal within a 10% margin of
error. During ring qualification, a timer is loaded with the RAS[5:0] field upon a TIP/RING
event and decrements at a regular rate. When a subsequent TIP/RING event occurs, the
timer value is compared to the RMX[5:0] field, and, if it exceeds the value in RMX[5:0], the
frequency of the ring is too high and the ring is invalidated. The difference between
RAS[5:0] and RMX[5:0] identifies the minimum duration between TIP/RING events to
qualify as a ring, in binary-coded increments of 2.0 ms (nominal). A TIP/RING event typi-
cally occurs twice per ring tone period. At 20 Hz, TIP/RING events would occur every
1/(2 x 20 Hz) = 25 ms. To calculate the correct RMX[5:0] value for a frequency range
[f_min, f_max], the following equation should be used:
To compensate for error margin and ensure a sufficient ring detection window, it is recom-
mended that the calculated value of RMX[5:0] be incremented by 1.
0
0
0
...
1
D6
RDLY[1:0]
RMX 5:0
D5
00
01
10
11
[
]
=
Rev. 1.0
RAS 5:0
D4
[
Delay
0 ms
256 ms
512 ms
1792 ms
]
Function
–
-------------------------------------------- - , RMX RAS
2 f_max
D3
×
RMX[5:0]
R/W
1
×
2 ms
D2
≤
D1
Si3068
D0
31