74LVC16374ADGG,112 NXP Semiconductors, 74LVC16374ADGG,112 Datasheet
74LVC16374ADGG,112
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74LVC16374ADGG,112 Summary of contents
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D-type flip-flop with 5 V tolerant inputs/outputs; 3-state Rev. 07 — 23 March 2010 1. General description The 74LVC16374A and 74LVCH16374A are 16-bit edge-triggered flip-flops featuring separate D-type inputs with bus hold (74LVCH16374A only) for each ...
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... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range −40 °C to +125 °C 74LVC16374ADL 74LVCH16374ADL −40 °C to +125 °C 74LVC16374ADGG 74LVCH16374ADGG −40 °C to +125 °C 74LVC16374ABQ 74LVCH16374ABQ 4. Functional diagram 1 1OE 2OE 47 1D0 46 1D1 44 1D2 43 1D3 41 1D4 40 1D5 38 1D6 ...
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... NXP Semiconductors 1D0 1CP 1OE Fig 3. Logic diagram Fig 4. Bus hold circuit 74LVC_LVCH16374A_7 Product data sheet 74LVC16374A; 74LVCH16374A 16-bit edge-triggered D-type flip-flop tolerant; 3-state 1Q0 2D0 FF1 2CP 2OE to 7 other channels V CC data input mna705 All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 5. Pin configuration SOT370-1 (SSOP48) and SOT362-1 (TSSOP48) 74LVC_LVCH16374A_7 Product data sheet 74LVC16374A; 74LVCH16374A 16-bit edge-triggered D-type flip-flop tolerant; 3-state 74LVC16374A 74LVCH16374A 1CP 1OE 1D0 1Q0 3 46 1D1 1Q1 4 45 GND GND 5 44 1D2 1Q2 ...
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... NXP Semiconductors terminal 1 index area (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 6. Pin configuration SOT1134-1 (HXQFN60U) 74LVC_LVCH16374A_7 Product data sheet 74LVC16374A; 74LVCH16374A 16-bit edge-triggered D-type flip-flop tolerant; 3-state 74LVC16374A ...
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... NXP Semiconductors 5.2 Pin description Table 2. Pin description Symbol Pin SOT370-1 and SOT362-1 1OE, 2OE 1, 24 GND 4, 10, 15, 21, 28, 34, 39 18, 31 1Q0 to 1Q7 11, 12 2Q0 to 2Q7 13, 14, 16, 17, 19, 20, 22, 23 1D0 to 1D7 47, 46, 44, 43, 41, 40, 38, 37 2D0 to 2D7 36, 35, 33, 32, 30, 29, 27, 26 ...
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... NXP Semiconductors Table 4. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter P total power dissipation tot [1] The minimum input voltage ratings may be exceeded if the input current ratings are observed. [2] The output voltage ratings may be exceeded if the output current ratings are observed. ...
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... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions V LOW-level output voltage = 100 μ input leakage current GND I I OFF-state output current GND power-off OFF CC leakage current I supply current V = 3.6 V ...
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... NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Symbol Parameter Conditions t propagation nCP to nQn; see pd delay enable time nOE to nQn; see disable time nOE to nQn; see dis pulse width nCP HIGH; see ...
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... NXP Semiconductors 11. Waveforms nCP input nQn output Measurement points are given in V and V are the typical output voltage levels that occur with the output load Fig 7. Clock (nCP) to output (nQn) propagation delays, clock pulse width, and the maximum frequency nCP input ...
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... NXP Semiconductors nOE input output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH Measurement points are given in V and V are the typical output voltage levels that occur with the output load Fig 9. 3-state enable and disable times Table 8. Measurement points Supply voltage Input 1.2 V ...
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... NXP Semiconductors Test data is given in Table Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance External voltage for measuring switching times. EXT Fig 10. Test circuit for measuring switching times Table 9. Test data ...
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... NXP Semiconductors 12. Package outline SSOP48: plastic shrink small outline package; 48 leads; body width 7 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.4 2.35 mm 2.8 0.25 0.2 2.20 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE ...
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... NXP Semiconductors TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6 pin 1 index 1 DIMENSIONS (mm are the original dimensions). A UNIT max. 0.15 1.05 mm 1.2 0.25 0.05 0.85 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors HXQFN60U: plastic thermal enhanced extremely thin quad flat package; no leads; 60 terminals; UTLP based; body 0.5 mm terminal 1 index area A10 terminal 1 index area D1 Dimensions Unit max 0.50 0.05 0.35 4.1 mm nom 0.48 0.02 0.30 4.0 min 0.46 0.00 0.25 3.9 ...
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... HXQFN60U (SOT1134-1) package. Product data sheet The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Added: type numbers 74LVC16374ABQ and 74LVCH16374ABQ (HUQFN60U package). ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... NXP Semiconductors 16. Contact information For more information, please visit: For sales office addresses, please send an email to: 74LVC_LVCH16374A_7 Product data sheet 74LVC16374A; 74LVCH16374A 16-bit edge-triggered D-type flip-flop tolerant; 3-state http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 07 — 23 March 2010 © ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 Functional description . . . . . . . . . . . . . . . . . . . 6 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 13 Abbreviations ...