si5319 Silicon Laboratories, si5319 Datasheet - Page 8

• Manufacturer Part Number: si5319
• Description: Any-rate Precision Clock Multiplier/jitter Attenuator
• Manufacturer: Silicon Laboratories

Si5319
8
Note: Internal register names are indicated by underlined italics (e.g., INT_PIN. See Si5319 Register Map).
5, 10,
Pin #
8, 31
32
15
16
17
18
21
22
11
7
6
Pin Name
RATE0
RATE1
CKIN+
CKIN–
GND
LOL
SCL
V
CS
XB
XA
DD
GND
V
I/O
O
DD
I
I
I
I
I
Signal Level
LVCMOS
LVCMOS
LVCMOS
3-Level
Analog
Supply
Supply
Multi
Supply.
The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass capaci-
tors should be associated with the following V
5
10
32
A 1.0 µF should also be placed as close to the device as is practical.
External Crystal or Reference Clock.
External crystal should be connected to these pins to use internal
oscillator based reference. Refer to the Family Reference Manual for
interfacing to an external reference. The external reference must be
from a high-quality clock source (TCXO, OCXO). Frequency of crystal
or external clock is set by the RATE pins.
Ground.
Must be connected to system ground. Minimize the ground path
impedance for optimal performance of this device.
External Crystal or Reference Clock Rate.
Three level inputs that select the type and rate of external crystal or
reference clock to be applied to the XA/XB port. Refer to the Family
Reference Manual for settings. These pins have both a weak pull-up
and a weak pull-down; they default to M. The "HH" setting is not sup-
ported.
Some designs may require an external resistor voltage divider when
driven by an active device that will tri-state.
Clock Input.
Differential input clock. This input can also be driven with a single-
ended signal. Input frequency range is 2 kHz to 710 MHz.
PLL Loss of Lock Indicator.
This pin functions as the active high PLL loss of lock indicator if the
LOL_PIN register bit is set to 1.
0 = PLL locked.
1 = PLL unlocked.
If LOL_PIN = 0, this pin will tristate. Active polarity is controlled by the
LOL_POL bit. The PLL lock status will always be reflected in the
LOL_INT read only register bit.
Xtal/Input Clock Select.
This pin selects the active DSPLL input clock, which can be a clock
input or a crystal input. See the FREE_EN register for free run settings.
0 = Select clock input (CKIN).
1 = Select crystal input.
This pin should not be left open.
Serial Clock/Serial Clock.
This pin functions as the serial clock input for both SPI and I
This pin has a weak pull-down.
Preliminary Rev. 0.3
0.1 µF
0.1 µF
0.1 µF
Description
DD
pins:
2
C modes.