74LVC823APW,118 NXP Semiconductors, 74LVC823APW,118 Datasheet - Page 5

• Manufacturer Part Number: 74LVC823APW,118
• Description: IC 9BIT D FF POS-EDGE 24TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74LVCr
• Type: D-Type Busr

Specifications of 74LVC823APW,118

• Package / Case: 24-TSSOP
• Function: Master Reset
• Output Type: Tri-State Non Inverted
• Number Of Elements: 1
• Number Of Bits Per Element: 9
• Frequency - Clock: 200MHz
• Delay Time - Propagation: 3.7ns
• Trigger Type: Positive Edge
• Current - Output High, Low: 24mA, 24mA
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Circuits: 1
• Logic Family: LVC
• Logic Type: D-Type Edge Triggered Flip-Flop
• Polarity: Non-Inverting
• Input Type: Single-Ended
• Propagation Delay Time: 5.1 ns at 3.3 V
• High Level Output Current: - 24 mA
• Supply Voltage (max): 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Voltage (min): 1.2 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 74LVC823APW-T; 74LVC823APW-T; 935262541118

Philips Semiconductors
6. Pinning information
9397 750 13128
Product data sheet
Fig 5. Pin configuration SO24 and (T)SSOP24.
GND
MR
OE
D0
D1
D2
D3
D4
D5
D6
D7
D8
10
11
12
1
2
3
4
5
6
7
8
9
6.1 Pinning
6.2 Pin description
Table 3:
Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
823
001aaa845
Pin description
Pin
OE
D0
D1
D2
D3
D4
D5
D6
D7
D8
MR
GND
CP
CE
Q8
Q7
Q6
24
23
22
21
20
19
18
17
16
15
14
13
V
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
CE
CP
CC
Description
output enable input (active LOW)
data input
data input
data input
data input
data input
data input
data input
data input
data input
master reset input (active LOW)
ground (0 V)
clock input (LOW-to-HIGH; edge-triggered)
clock enable input (active LOW)
3-state flip-flop output
3-state flip-flop output
3-state flip-flop output
Rev. 02 — 10 May 2004
9-bit D-type flip-flop with 5 V tolerant inputs/outputs
Fig 6. Pin configuration DHVQFN24.
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
a supply pin or input.
index area
terminal 1
MR
D0
D1
D2
D3
D4
D5
D6
D7
D8
10
11
2
3
4
5
6
7
8
9
Transparent top view
GND
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
(1)
823
74LVC823A
23
22
21
20
19
18
17
16
15
14
001aaa846
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
CE
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