74AUP2G80GT,115 NXP Semiconductors, 74AUP2G80GT,115 Datasheet - Page 12
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74AUP2G80GT,115
Manufacturer Part Number
74AUP2G80GT,115
Description
IC DUAL D-TYPE F-F 8-XSON
Manufacturer
NXP Semiconductors
Series
74AUPr
Type
D-Typer
Datasheet
1.74AUP2G80GD125.pdf
(24 pages)
Specifications of 74AUP2G80GT,115
Function
Standard
Output Type
Inverted
Number Of Elements
2
Number Of Bits Per Element
1
Frequency - Clock
550MHz
Delay Time - Propagation
2.2ns
Trigger Type
Positive Edge
Current - Output High, Low
4mA, 4mA
Voltage - Supply
0.8 V ~ 3.6 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
8-XSON
Logic Family
AUP
Technology
CMOS
Number Of Bits
2
Number Of Elements
2
Clock-edge Trigger Type
Positive-Edge
Polarity
Inverting
Operating Supply Voltage (typ)
1.8/2.5/3.3V
Propagation Delay Time
27.2ns
Low Level Output Current
4mA
High Level Output Current
-4mA
Operating Supply Voltage (min)
0.8V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74AUP2G80GT-G
74AUP2G80GT-G
935280723115
74AUP2G80GT-G
935280723115
NXP Semiconductors
12. Waveforms
Table 9.
74AUP2G80
Product data sheet
Supply voltage
V
0.8 V to 3.6 V
Fig 8.
Fig 9.
CC
Measurement points are given in
Logic levels: V
The clock input (nCP) to output (nQ) propagation delays
Measurement points are given in
Logic levels: V
The clock input (nCP) to output (nQ) propagation delays, clock pulse width, nD to nCP setup and hold
times and the nCP maximum frequency
Measurement points
OL
OL
and V
and V
nCP input
nQ output
nD input
Output
V
0.5 × V
OH
OH
M
nCP input
nQ output
nD input
are typical output voltage levels that occur with the output load.
are typical output voltage levels that occur with the output load.
GND
GND
V
V
CC
OH
OL
V
V
I
I
Table
Table
GND
GND
V
V
OH
OL
All information provided in this document is subject to legal disclaimers.
V
V
I
I
9.
9.
V
M
t
Rev. 5 — 5 October 2010
su(L)
V
Input
V
0.5 × V
M
M
t
t
V
V
PLH
h
M
M
Low-power dual D-type flip-flop; positive-edge trigger
CC
t
t
PLH
V
W
M
1/f
max
V
t
su(H)
M
V
V
I
CC
t
PHL
V
M
t
h
001aaf311
t
PHL
001aaf312
74AUP2G80
t
≤ 3.0 ns
r
= t
© NXP B.V. 2010. All rights reserved.
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