74ALVC74D,118 NXP Semiconductors, 74ALVC74D,118 Datasheet - Page 4
![IC DUAL D F-F POS-EDGE 14SOIC](/photos/6/57/65749/14-soic-sot108-1_sml.jpg)
74ALVC74D,118
Manufacturer Part Number
74ALVC74D,118
Description
IC DUAL D F-F POS-EDGE 14SOIC
Manufacturer
NXP Semiconductors
Series
74ALVCr
Type
D-Typer
Datasheet
1.74ALVC74PW118.pdf
(20 pages)
Specifications of 74ALVC74D,118
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Function
Set(Preset) and Reset
Output Type
Differential
Number Of Elements
2
Number Of Bits Per Element
1
Frequency - Clock
275MHz
Delay Time - Propagation
3.7ns
Trigger Type
Positive Edge
Current - Output High, Low
24mA, 24mA
Voltage - Supply
1.65 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Number Of Circuits
2
Logic Family
ALVC
Logic Type
D-Type Edge Triggered Flip-Flop
Polarity
Inverting/Non-Inverting
Input Type
Single-Ended
Propagation Delay Time
2.3 ns at 3.3 V
High Level Output Current
- 24 mA
Supply Voltage (max)
3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Supply Voltage (min)
1.65 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
74ALVC74D-T
74ALVC74D-T
935269741118
74ALVC74D-T
935269741118
Philips Semiconductors
PINNING
2003 May 26
handbook, halfpage
PIN
Dual D-type flip-flop with set and reset;
positive-edge trigger
10
11
12
13
14
(1) The die substrate is attached to this pad using conductive die
1
2
3
4
5
6
7
8
9
attach material. It can not be used as a supply pin or input.
1RD
1D
1CP
1SD
1Q
1Q
GND
2Q
2Q
2SD
2CP
2D
2RD
V
SYMBOL
Fig.2 Pin configuration DHVQFN14.
1CP
1SD
CC
1Q
1Q
1D
Top view
2
3
4
5
6
asynchronous reset-direct input
(active LOW)
data input
clock input (LOW-to-HIGH,
edge-triggered)
asynchronous set-direct input
(active LOW)
true flip-flop output
complement flip-flop output
ground (0 V)
complement flip-flop output
true flip-flop output
asynchronous set-direct input
(active LOW)
clock input (LOW-to-HIGH,
edge-triggered)
data input
asynchronous reset-direct input
(active LOW)
supply voltage
GND
1RD
GND
7
1
V CC
(1)
2Q
14
8
DESCRIPTION
MDB105
13
12
11
10
9
2RD
2D
2CP
2SD
2Q
4
handbook, halfpage
handbook, halfpage
Fig.1 Pin configuration SO14 and TSSOP14.
GND
1RD
1CP
1SD
1D
1Q
1Q
12
11
2
3
Fig.3 Logic symbol.
1
2
3
4
5
6
7
1CP
2CP
1D
2D
1RD 2RD
1SD
D
CP
74
4 10
1 13
RD
SD
FF
MNA417
2SD
Q
Q
1Q
2Q
1Q
2Q
MNA418
14
13
12
11
10
9
8
Product specification
V CC
2RD
2D
2CP
2SD
2Q
2Q
74ALVC74
5
9
6
8