N74F574D,602 NXP Semiconductors, N74F574D,602 Datasheet - Page 2

• Manufacturer Part Number: N74F574D,602
• Description: IC FLIP FLOP TRI-ST OCTAL 20SOIC
• Manufacturer: NXP Semiconductors
• Series: 74Fr
• Type: D-Type Busr

Specifications of N74F574D,602

• Function: Standard
• Output Type: Tri-State Non Inverted
• Number Of Elements: 1
• Number Of Bits Per Element: 8
• Frequency - Clock: 100MHz
• Delay Time - Propagation: 3.2ns
• Trigger Type: Positive Edge
• Current - Output High, Low: 3mA, 24mA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Number Of Circuits: 8
• Logic Family: F
• Logic Type: TTL
• Polarity: Non-Inverting
• Input Type: Single-Ended
• Propagation Delay Time: 5 ns
• High Level Output Current: - 3 mA
• Supply Voltage (max): 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Supply Voltage (min): 4.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 933911720602; N74F574D; N74F574D

Philips Semiconductors
FEATURES
DESCRIPTION
The 74F573 is an octal transparent latch coupled to eight 3-State
output buffers. The two sections of the device are controlled
independently by Enable (E) and Output Enable (OE) control gates.
The 74F573 is functionally identical to the 74F373 but has a
broadside pinout configuration to facilitate PC board layout and
allow easy interface with microprocessors.
The data on the D inputs is transferred to the latch outputs when the
Enable (E) input is High. The latch remains transparent to the data
input while E is High and stores the data that is present one setup
time before the High-to-Low enable transition.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active Low Output Enable (OE) controls all eight 3-State buffers
independent to the latch operation. When OE is Low, the latched or
transparent data appears at the outputs. When OE is High, the
outputs are in high impedance “off” state, which means they will
neither drive nor load the bus.
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
NOTE: One (1.0) FAST Unit Load is defined as: 20 A in the High state and 0.6mA in the Low state.
D0 - D7
E (74F573)
OE
CP (74F574)
Q0 - Q7
1989 Oct 16
74F573 is broadside pinout version of 74F373
74F574 is broadside pinout version of 74F374
Inputs and Outputs on opposite side of package allow easy
interface to Microprocessors
Useful as an Input or Output port for Microprocessors
3-State Outputs for Bus interfacing
Common Output Enable
74F563 and 74F564 are inverting version of 74F573 and 74F574
respectively
3-State Outputs glitch free during power-up and power-down
These are High-Speed replacements for N8TS805 and N8TS806
Latch/flip-flop
74F573 Octal Transparent Latch (3-State)
74F574 Octal D Flip-Flop (3-State)
PINS
Data inputs
Latch Enable input (active falling edge)
Output Enable input (active Low)
Clock Pulse input (active rising edge)
3-State outputs
DESCRIPTION
2
The 74F574 is functionally identical to the 74F374 but has a
broadside pinout configuration to facilitate PC board layout and
allow easy interface with microprocesors.
It is an 8-bit, edge triggered register coupled to eight 3-State output
buffers. The two sections of the device are controlled independently
by the clock (CP) and Output Enable (OE) control gates.
The register is fully edge-triggered. The state of each D input, one
setup time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active Low Output Enable (OE) controls all eight 3-State buffers
independently of the latch operation. When OE is Low, the latched
or transparent data appears at the outputs. When OE is High, the
outputs are in high impedance “off” state, which means they will
neither drive nor load the bus.
ORDERING INFORMATION
20-Pin Plastic DIP
20-Pin Plastic SOL
20-Pin Plastic SSOP
74F573
74F574
TYPE
TYPE
DESCRIPTION
PROPAGATION DELAY
TYPICAL f
TYPICAL
180MHz
5.0ns
COMMERCIAL RANGE
N74F573N, N74F574N
N74F573D, N74F574D
T
amb
V
MAX
CC
N74F573DB
HIGH/LOW
74F (U.L.)
= 0 C to +70 C
= 5V 10%,
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
150/40
74F573/74F574
TYPICAL SUPPLY
TYPICAL SUPPLY
Product specification
CURRENT
CURRENT
(TOTAL)
(TOTAL)
LOAD VALUE
853-0083 97897
35mA
50mA
3.0mA/24mA
20 A/0.6mA
20 A/0.6mA
20 A/0.6mA
20 A/0.6mA
HIGH/LOW
SOT146-1
SOT163-1
SOT339-1
PKG DWG #