74AUP1G80GF,132 NXP Semiconductors, 74AUP1G80GF,132 Datasheet - Page 11
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74AUP1G80GF,132
Manufacturer Part Number
74AUP1G80GF,132
Description
IC FLIP-FLOP D POS-EDGE 6-XSON
Manufacturer
NXP Semiconductors
Series
74AUPr
Type
D-Typer
Datasheet
1.74AUP1G80GF132.pdf
(21 pages)
Specifications of 74AUP1G80GF,132
Output Type
Inverted
Package / Case
6-XSON, SOT891
Function
Standard
Number Of Elements
1
Number Of Bits Per Element
1
Frequency - Clock
550MHz
Delay Time - Propagation
2.2ns
Trigger Type
Positive Edge
Current - Output High, Low
4mA, 4mA
Voltage - Supply
0.8 V ~ 3.6 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Number Of Circuits
1
Logic Family
AUP
Logic Type
CMOS
Polarity
Inverting
Input Type
Single-Ended
Propagation Delay Time
20.7 ns
High Level Output Current
- 4 mA
Low Level Output Current
4 mA
Supply Voltage (max)
3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Supply Voltage (min)
0.8 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
74AUP1G80GF-H
74AUP1G80GF-H
935281118132
74AUP1G80GF-H
935281118132
NXP Semiconductors
12. Waveforms
Table 9.
74AUP1G80
Product data sheet
Supply voltage
V
0.8 V to 3.6 V
Fig 7.
Fig 8.
CC
Measurement points are given in
Logic levels: V
The clock input (CP) to output (Q) propagation delays
Measurement points are given in
Logic levels: V
The clock input (CP) to output (Q) propagation delays, clock pulse width, D to CP set-up and hold times
and the maximum input clock frequency
Measurement points
OL
OL
and V
and V
CP input
Q output
D input
Output
V
0.5 × V
OH
OH
M
CP input
Q output
D input
are typical output voltage drop that occur with the output load.
are typical output voltage drop that occur with the output load.
GND
GND
V
V
CC
OH
OL
V
V
Table
I
I
Table
GND
GND
V
V
All information provided in this document is subject to legal disclaimers.
OH
OL
V
V
I
I
9.
9.
Rev. 2 — 15 September 2010
V
M
Input
V
0.5 × V
V
M
M
t
t
V
su(L)
V
h
M
M
t
CC
PLH
V
t
W
M
t
PLH
Low-power D-type flip-flop; positive-edge trigger
1/f
max
V
M
V
V
I
CC
V
M
t
PHL
t
t
su(H)
h
mna652
mna653
t
PHL
74AUP1G80
t
≤ 3.0 ns
r
= t
© NXP B.V. 2010. All rights reserved.
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