mrf89xa Microchip Technology Inc., mrf89xa Datasheet - Page 60

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mrf89xa

Manufacturer Part Number
mrf89xa
Description
Ultra-low Power, Integrated Ism Band Sub-ghz Transceiver
Manufacturer
Microchip Technology Inc.
Datasheet

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3.1
A power-on reset of the MRF89XA is triggered at power
up. Additionally, a manual reset can be issued by
controlling the TEST8 pin (pin 13).
3.1.1
If the application requires the disconnection of V
from the MRF89XA, the user should wait for 10 ms
from the end of the POR cycle before commencing
communications using SPI. The TEST8 pin should be
left floating during the POR sequence. Figure 3-2 illus-
trates the POR Timing..
FIGURE 3-2:
FIGURE 3-3:
DS70622B-page 60
MRF89XA
Note:
Reset of the Chip
POWER-ON RESET (POR)
Any CLKOUT-related activity can also be
used to detect that the chip is ready.
Pin 13
(input)
V
DD
Pin 13
(output)
V
POR TIMING DIAGRAM
MANUAL RESET TIMING DIAGRAM
DD
Undefined
High-Z
> 100 µs
Wait for
10 ms
Preliminary
DD
1
Chip is ready from this point forward
High-Z
Wait for
5 ms
3.1.2
A manual reset of the MRF89XA is possible even for
applications in which V
disconnected. The TEST8 pin should be pulled high for
100 u (micro) and then released. The user should then
wait 5 ms before using the chip. The pin is driven with
an open-drain output, and therefore, is pulled high
while the device is in POR. Figure 3-3 illustrates the
Manual Reset Timing
Note:
Chip is ready from this point forward
MANUAL RESET
When the TEST8 pin is driven high, an
current consumption of up to 10 mA can
be seen on V
© 2010 Microchip Technology Inc.
DD
DD
.
cannot be physically

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