mrf89xa Microchip Technology Inc., mrf89xa Datasheet - Page 20

• Manufacturer Part Number: mrf89xa
• Description: Ultra-low Power, Integrated Ism Band Sub-ghz Transceiver
• Manufacturer: Microchip Technology Inc.

2.9.1
Figure 2-6 illustrates the transmitter architecture block
diagram. The baseband I and Q signals are digitally
generated
Converters (DAC) followed by two anti-aliasing
low-pass filters transform the digital signal into analog
in-phase (I) and quadrature (Q) components whose
frequency is the selected frequency deviation (set by
using the FDVAL<7:0> bits from FDEVREG<7:0>).
In FSK mode, the relative phase of I and Q is switched
by the input data between -90° and +90° with
continuous phase. The modulation is therefore
performed at this initial stage, because the information
contained in the phase difference will be converted into
a frequency shift when the I and Q signals are
up-converted in the first mixer stage. This first
up-conversion stage is duplicated to enhance image
rejection. The FSK convention is such that:
In OOK mode, the phase difference between the I and
Q channels is kept constant (independent of the
transmitted data). Thus, the first stage of up-conversion
creates a fixed frequency signal at the low IF = f
(This explains why the transmitted OOK spectrum is
offset by f
switching the PA and PA regulator stages ON and OFF.
By convention:
FIGURE 2-7:
DS70622B-page 20
MRF89XA
DATA = 1 →f
DATA = 0 →f
DATA = 1 →PAon
DATA = 0 →PAoff
dev
TRANSMITTER ARCHITECTURE
by
). OOK Modulation is accomplished by
rf
rf
a
+ f
– f
DDS
dev
dev
I(t), Q(t) Signals Overview
whose
Digital-to-Analog
Preliminary
dev
Fdev
1
After the interpolation filters, a set of four mixers
combines the I and Q signals and converts them into a
pair of complex signals at the second intermediate
frequency, equal to one-eighth of the LO frequency, or
one-ninth of the RF frequency. These two new I and Q
signals are then combined and up-converted to the
final RF frequency by two quadrature mixers fed by the
LO signal. The signal is pre-amplified, and then the
transmitter output is driven by a final power amplifier
stage.
The FIFO is 1 byte (8 bits) wide; therefore, it only
performs byte (parallel) operations, whereas the
demodulator functions serially. A Shift register is
employed to interface the two FIFO and Demodulator
blocks. In Transmit mode, it takes bytes from the FIFO
and outputs them serially (MSB first) at the
programmed bit rate to the modulator. Similarly, in
Receive mode, the shift register gets bit-by-bit data
from the demodulator and writes them byte-by-byte to
the FIFO.These details are illustrated in Figure 2-7.
I(t)
Q(t)
© 2010 Microchip Technology Inc.